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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fabs.mir19 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
20 ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
25 ; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
26 ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
32 ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32)
49 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
55 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
61 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
231 ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
237 ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
[all …]
H A Dcombine-fabs-fneg.mir16 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[TRUNC]]
17 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FABS]](s16)
38 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
39 ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](s32)
57 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
58 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
76 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[COPY]]
77 ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
95 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(<3 x s32>) = G_FABS [[COPY]]
96 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[FABS]](<3 x s32>)
H A Dinst-select-fabs.mir117 ; GCN: $vgpr0 = COPY [[FABS]](s32)
123 ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
129 ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
135 ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32)
141 ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](s32)
412 ; GCN: $vgpr0 = COPY [[FABS]](<2 x s16>)
418 ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
424 ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
581 ; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
587 ; SI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
[all …]
H A Dregbankselect-fabs.mir16 ; CHECK-NEXT: [[FABS:%[0-9]+]]:sgpr(s32) = G_FABS [[COPY]]
17 ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](s32)
34 ; CHECK-NEXT: [[FABS:%[0-9]+]]:vgpr(s32) = G_FABS [[COPY]]
35 ; CHECK-NEXT: $vgpr0 = COPY [[FABS]](s32)
H A Dlegalize-intrinsic-amdgcn-fdiv-fast.mir15 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY1]]
19 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
43 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[COPY1]]
47 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
H A Dlegalize-intrinsic-round.mir20 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
37 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
54 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
164 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
182 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
200 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
229 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
256 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
283 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[FSUB]]
341 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
[all …]
H A Dinst-select-fneg.mir722 ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
730 ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
738 ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
746 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
754 ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
1043 ; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
1225 ; GCN: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
1236 ; SI-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
1247 ; VI-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
1258 ; GFX9-NEXT: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
[all …]
H A Dlegalize-fptosi.mir423 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
426 ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
446 ; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
449 ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
481 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
484 ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
521 ; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
524 ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
724 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[INTRINSIC_TRUNC]]
727 ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FABS]], [[C1]]
[all …]
H A Dlegalize-frint.mir79 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
80 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
195 ; SI-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[UV]]
196 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfabs.ll31 ; CHECK-NEXT: ret double [[FABS]]
76 ; CHECK-NEXT: ret double [[FABS]]
136 ; CHECK-NEXT: ret float [[FABS]]
148 ; CHECK-NEXT: ret float [[FABS]]
160 ; CHECK-NEXT: ret float [[FABS]]
183 ; CHECK-NEXT: ret float [[FABS]]
244 ; CHECK-NEXT: ret double [[FABS]]
429 ; CHECK-NEXT: ret half [[FABS]]
800 ; CHECK-NEXT: ret half [[FABS]]
815 ; CHECK-NEXT: ret half [[FABS]]
[all …]
H A Dfast-math.ll637 ; CHECK-NEXT: ret double [[FABS]]
651 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
664 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
677 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
690 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
703 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
716 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
773 ; CHECK-NEXT: [[FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X:%.*]])
774 ; CHECK-NEXT: ret float [[FABS]]
784 ; CHECK-NEXT: ret double [[FABS]]
[all …]
H A Dsqrt-nofast.ll35 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[A:%.*]])
36 ; CHECK-NEXT: ret double [[FABS]]
H A Dfloat-shrink-compare.ll34 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
35 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
47 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
48 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
243 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
244 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
256 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
257 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
H A Dknown-never-nan.ll12 ; CHECK-NEXT: [[FABS:%.*]] = call double @llvm.fabs.f64(double [[ARG0:%.*]])
13 ; CHECK-NEXT: [[OP:%.*]] = call double @llvm.sqrt.f64(double [[FABS]])
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfabs.mir21 ; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
22 ; FP32: $f0 = COPY [[FABS]](s32)
27 ; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
28 ; FP64: $f0 = COPY [[FABS]](s32)
47 ; FP32: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
48 ; FP32: $d0 = COPY [[FABS]](s64)
53 ; FP64: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
54 ; FP64: $d0 = COPY [[FABS]](s64)
H A Dfabs_vec.mir22 ; P5600: [[FABS:%[0-9]+]]:_(<4 x s32>) = G_FABS [[LOAD]]
23 ; P5600: G_STORE [[FABS]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
46 ; P5600: [[FABS:%[0-9]+]]:_(<2 x s64>) = G_FABS [[LOAD]]
47 ; P5600: G_STORE [[FABS]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfabs.mir22 ; FP32: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
23 ; FP32: $f0 = COPY [[FABS]](s32)
28 ; FP64: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
29 ; FP64: $f0 = COPY [[FABS]](s32)
49 ; FP32: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
50 ; FP32: $d0 = COPY [[FABS]](s64)
55 ; FP64: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
56 ; FP64: $d0 = COPY [[FABS]](s64)
H A Dfabs_vec.mir23 ; P5600: [[FABS:%[0-9]+]]:fprb(<4 x s32>) = G_FABS [[LOAD]]
24 ; P5600: G_STORE [[FABS]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)
48 ; P5600: [[FABS:%[0-9]+]]:fprb(<2 x s64>) = G_FABS [[LOAD]]
49 ; P5600: G_STORE [[FABS]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dfloating-point-arithmetic.ll257 ; CHECK-NEXT: ret float [[FABS]]
283 ; CHECK-NEXT: ret float [[FABS]]
309 ; CHECK-NEXT: ret float [[FABS]]
359 ; CHECK-NEXT: ret float [[FABS]]
385 ; CHECK-NEXT: ret float [[FABS]]
411 ; CHECK-NEXT: ret float [[FABS]]
437 ; CHECK-NEXT: ret float [[FABS]]
464 ; CHECK-NEXT: ret float [[FABS]]
476 ; CHECK-NEXT: ret float [[FABS]]
488 ; CHECK-NEXT: ret float [[FABS]]
[all …]
H A Dfloating-point-arithmetic-strictfp.ll220 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SQRT]])
221 ; CHECK-NEXT: ret float [[FABS]]
233 ; CHECK-NEXT: ret float [[FABS]]
245 ; CHECK-NEXT: ret float [[FABS]]
257 ; CHECK-NEXT: ret float [[FABS]]
270 ; CHECK-NEXT: ret float [[FABS]]
458 ; CHECK-NEXT: ret float [[FABS]]
470 ; CHECK-NEXT: ret float [[FABS]]
484 ; CHECK-NEXT: ret float [[FABS]]
499 ; CHECK-NEXT: ret float [[FABS]]
[all …]
H A Dknown-never-nan.ll59 ; CHECK-NEXT: [[FABS:%.*]] = call double @llvm.fabs.f64(double [[ARG0:%.*]])
60 ; CHECK-NEXT: [[OP:%.*]] = call double @llvm.sqrt.f64(double [[FABS]])
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcombine-fabs.mir12 ; CHECK: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
13 ; CHECK: $w0 = COPY [[FABS]](s32)
26 ; CHECK: [[FABS:%[0-9]+]]:_(<2 x s32>) = G_FABS [[COPY]]
27 ; CHECK: $x0 = COPY [[FABS]](<2 x s32>)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
5 ; If the FABS() result isn't used, the AND instruction should be eliminated.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h912 FABS, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp396 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in AMDGPUTargetLowering()
476 ISD::FABS, ISD::AssertZext, in AMDGPUTargetLowering()
1648 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1651 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2130 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2165 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2542 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
3553 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) || in foldFreeOpFromSelect()
3560 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3581 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL) in foldFreeOpFromSelect()
[all …]

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