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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darmv8a-fpmul.s36 VFMAL.F16 D0, S1, S2
39 VFMSL.F16 Q0, D1, D2
41 VFMAL.F16 D0, S1, S2[1]
44 VFMSL.F16 Q0, D1, D2[3]
H A Darmv8a-fpmul-error.s3 VFMAL.F16 D0, S1, S2[2]
7 VFMSL.F16 Q0, D1, D2[4]
9 VFMSL.F16 D0, S1, S16[0]
11 VFMSL.F16 Q0, D1, D8[0]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll4 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-F16-NOFTZ %s
14 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16-FTZ %s
86 ; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
88 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
102 ; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
104 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
134 ; CHECK-F16-NOFTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000
136 ; CHECK-F16-FTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000
171 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F0:%f[0-9]+]], [[A]];
172 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F1:%f[0-9]+]], [[B]];
[all …]
H A Df16x2-instructions.ll79 ; CHECK-F16-NEXT: add.rn.f16x2 [[R:%hh[0-9]+]], [[A]], [[B]];
104 ; CHECK-F16: mov.u32 [[I:%r[0-9+]]], 1073757184;
105 ; CHECK-F16: mov.b32 [[IHH:%hh[0-9+]]], [[I]];
106 ; CHECK-F16: add.rn.f16x2 [[R:%hh[0-9]+]], [[A]], [[IHH]];
127 ; CHECK-F16: mov.u32 [[I:%r[0-9+]]], 1073757184;
128 ; CHECK-F16: mov.b32 [[IHH:%hh[0-9+]]], [[I]];
129 ; CHECK-F16: add.rn.f16x2 [[R:%hh[0-9]+]], [[B]], [[IHH]];
151 ; CHECK-F16-NEXT: sub.rn.f16x2 [[R:%hh[0-9]+]], [[A]], [[B]];
175 ; CHECK-F16: mov.u32 [[I0:%r[0-9+]]], 0;
176 ; CHECK-F16: mov.b32 [[IHH0:%hh[0-9+]]], [[I0]];
[all …]
H A Dmath-intrins.ll2 ; RUN: llc < %s -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK,CHECK-F16
209 ; CHECK-F16: min.f16
253 ; CHECK-F16: min.f16x2
263 ; CHECK-F16: max.f16
307 ; CHECK-F16: max.f16x2
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/instructions/
H A Dfloat-casts.ll26 ; CHECK-DAG: [[F16:%.*]] = OpTypeFloat 16
28 ; CHECK-DAG: [[F16v2:%.*]] = OpTypeVector [[F16]] 2
30 ; CHECK-DAG: [[F16v3:%.*]] = OpTypeVector [[F16]] 3
39 ; CHECK: [[TRUNC32_16]] = OpFunction [[F16]]
42 ; CHECK: [[R:%.*]] = OpFConvert [[F16]] [[A]]
51 ; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
117 ; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
128 ; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
139 ; CHECK-NEXT: [[A:%.*]] = OpFunctionParameter [[F16]]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dhalf.ll2 …lc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-F16
40 ; CHECK-F16: vcvtb.f32.f16
53 ; CHECK-F16: vcvtb.f32.f16
54 ; CHECK-F16: vcvt.f64.f32
67 ; CHECK-F16: vcvtb.f16.f32
79 ; CHECK-F16: bl ___truncdfhf2
/llvm-project-15.0.7/mlir/python/mlir/runtime/
H A Dnp_to_memref.py21 class F16(ctypes.Structure): class
33 return F16
43 if array.dtype == F16:
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Darith-fp.ll19 %F16 = fadd half undef, undef
51 %F16 = fsub half undef, undef
82 %F16 = fsub half -0.0, undef
114 %F16 = fneg half undef
147 %F16 = fmul half undef, undef
179 %F16 = fdiv half undef, undef
211 %F16 = frem half undef, undef
243 %F16 = call half @llvm.sqrt.f16(half undef)
275 %F16 = call half @llvm.fabs.f16(half undef)
307 %F16 = call half @llvm.copysign.f16(half undef, half undef)
[all …]
H A Dmin-max.ll202 ; CHECK-F16-LABEL: 'minnum16'
203 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call half @llvm…
208 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
227 ; CHECK-F16-LABEL: 'maxnum16'
228 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call half @llvm…
233 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
295 ; CHECK-F16-LABEL: 'minimum16'
296 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call half @llvm…
301 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
320 ; CHECK-F16-LABEL: 'maximum16'
[all …]
H A Dreduce-minmax.ll169 ; CHECK-F16-LABEL: 'reduce_fmin16'
170 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2f16 = call half @ll…
171 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4f16 = call half @ll…
172 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8f16 = call half @ll…
173 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16f16 = call half @l…
174 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
191 ; CHECK-F16-LABEL: 'reduce_fmax16'
192 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2f16 = call half @ll…
193 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4f16 = call half @ll…
194 ; CHECK-F16-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8f16 = call half @ll…
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Dialect/AMDGPU/
H A DAMDGPU.td44 Results<(outs AnyTypeOf<[BF16, F16, F32, I32, I8,
46 VectorOfLengthAndType<[2, 4, 8], [F16, BF16]>,
92 Arguments<(ins AnyTypeOf<[BF16, F16, F32, I32, I8,
94 VectorOfLengthAndType<[2, 4, 8], [F16, BF16]>,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1067 // ASIMD FP divide, D-form, F16
1073 // ASIMD FP divide, Q-form, F16
1108 // ASIMD FP round, Q-form F16
1111 // ASIMD FP square root, D-form, F16
1117 // ASIMD FP square root, Q-form, F16
1920 // Floating point convert, long or narrow (F16 to F32 or F32 to F16)
1926 // or F64 to F16)
1934 // Floating point base2 log, F16
1957 // Floating point divide, F16
1999 // Floating point reduction, F16
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/readability/
H A Davoid-const-params-in-decls.cpp73 void F16(const A<const int> *const);
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td179 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>;
205 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
272 def Q4 : Rq<16, "F16", [D8, D9]>;
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td956 : F16<0b1001010000001001, (outs), (ins), "ijmp", []>,
961 : F16<0b1001010000011001, (outs), (ins), "eijmp", []>,
983 : F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>,
1654 : F16<0b1001010111001000, (outs), (ins), "lpm", []>,
1695 : F16<0b1001010111011000, (outs), (ins), "elpm", []>,
1731 : F16<0b1001010111101000, (outs), (ins), "spm", []>,
1734 let Defs = [R31R30] in def SPMZPi : F16<0b1001010111111000, (outs),
2170 def BREAK : F16<0b1001010110011000, (outs), (ins), "break", []>,
2177 def NOP : F16<0b0000000000000000, (outs), (ins), "nop", []>;
2183 def SLEEP : F16<0b1001010110001000, (outs), (ins), "sleep", []>;
[all …]
/llvm-project-15.0.7/mlir/include/mlir/ExecutionEngine/
H A DSparseTensorUtils.h95 DO(F16, f16) \
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td275 def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
289 R29, R30, R31, F14, F15, F16, F17, F18,
299 X29, X30, X31, F14, F15, F16, F17, F18,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallingConv.td153 F16, F17, F18, F19],
283 F14, F15, F16, F17, F18, F19]>>>,
287 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULibFunc.cpp637 res.ArgType = AMDGPULibFunc::F16; break; in parseItaniumParam()
740 case AMDGPULibFunc::F16: return "Dh"; in getItaniumTypeName()
891 case AMDGPULibFunc::F16: T = Type::getHalfTy(C); break; in getIntrinsicParamType()
H A DAMDGPULibFunc.h271 F16 = FLOAT | B16, enumerator
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DAMDGPUMetadata.h106 F16 = 5, enumerator
/llvm-project-15.0.7/mlir/include/mlir/Dialect/GPU/IR/
H A DGPUOps.td1095 let arguments = (ins Arg<MemRefOf<[F16, F32]>, "", [MemRead]>:$srcMemref,
1133 let arguments = (ins Arg<MMAMatrixOf<[F16, F32]>>:$src,
1134 Arg<MemRefOf<[F16, F32]>, "",[MemWrite]>:$dstMemref,
1170 let arguments = (ins Arg<MMAMatrixOf<[F16, F32]>>:$opA,
1171 Arg<MMAMatrixOf<[F16, F32]>>:$opB,
1172 Arg<MMAMatrixOf<[F16, F32]>>:$opC);
1212 let arguments = (ins AnyTypeOf<[F16, F32]>:$value);
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Tosa/IR/
H A DTosaTypesBase.td88 F16,
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td119 def F16 : LoongArchReg32<16,"f16", ["ft8"]>, DwarfRegNum<[48]>;

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