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Searched refs:EnableSubRegLiveness (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp32 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
207 return EnableSubRegLiveness; in enableSubRegLiveness()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp72 static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
389 if (EnableSubRegLiveness.getNumOccurrences()) in enableSubRegLiveness()
390 return EnableSubRegLiveness; in enableSubRegLiveness()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp37 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, variable
45 EnableSubRegLiveness) { in MachineRegisterInfo()