Searched refs:EltRC (Results 1 – 2 of 2) sorted by relevance
1994 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo() local1997 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()2000 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64 in expandPostRAPseudo()2820 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass; in insertSelect() local2829 EltRC = &AMDGPU::SGPR_32RegClass; in insertSelect()2832 EltRC = &AMDGPU::SGPR_64RegClass; in insertSelect()2845 Register DstElt = MRI.createVirtualRegister(EltRC); in insertSelect()
5468 const TargetRegisterClass *EltRC = getRegClassForTypeOnBank(EltTy, EltRB); in tryOptBuildVecToSubregToReg() local5469 if (!EltRC) in tryOptBuildVecToSubregToReg()5475 if (!getSubRegForClass(EltRC, TRI, SubReg)) in tryOptBuildVecToSubregToReg()