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Searched refs:EXTR (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_vector_instrs.ll48 ; CHECK-NEXT: [[EXTR:%.*]] = extractelement <2 x i16> [[ZEXTA]], i32 0
49 ; CHECK-NEXT: [[INSR:%.*]] = insertelement <2 x i16> [[ZEXTB]], i16 [[EXTR]], i32 1
77 ; CHECK-NEXT: [[EXTR:%.*]] = extractelement <2 x i16> [[LSHR]], i32 1
78 ; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[EXTR]], 5
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td30 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
H A DAArch64SchedPredExynos.td140 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedCyclone.td176 // EXTR Shifts a pair of registers and requires two micro-ops.
178 // EXTR Xn, Xm, #imm
184 // EXTR's first register read is delayed by one cycle, effectively
186 // EXTR Xn, Xm, #imm
H A DAArch64SchedAmpere1.td596 def : WriteRes<WriteExtr, [Ampere1UnitB]>; // EXTR shifts a reg pair
980 def : InstRW<[Ampere1Write_1cyc_1B], (instregex "EXTR(W|X)")>;
H A DAArch64ISelLowering.h153 EXTR, enumerator
H A DAArch64SchedA55.td70 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
H A DAArch64SchedTSV110.td408 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^EXTR(W|X)rri$")>;
H A DAArch64SchedFalkorDetails.td1208 def : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^EXTR(W|X)rri$")>;
H A DAArch64SchedNeoverseN2.td703 // NOTE: We don't model the difference between EXTR where both operands are the
H A DAArch64ISelLowering.cpp2125 MAKE_CASE(AArch64ISD::EXTR) in getTargetNodeName()
14654 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, in tryCombineToEXTR()
H A DAArch64InstrInfo.td2182 defm EXTR : ExtractImm<"extr">;
H A DAArch64InstrFormats.td2776 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-extract.ll46 ; this pattern to a single EXTR.
H A Dextract.ll46 ; this pattern to a single EXTR.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td280 // EXTR.W sub-class format (type 1).