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Searched refs:EX1 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td28 // EX1: address generation shifts
33 // There are shifters in both EX1 and EX2, and some instructions can be
181 def M7Read_ISS : SchedReadAdvance<-1>; // operands needed at EX1
208 let Latency = 0; // Update is bypassable out of EX1
332 // Treat pure shift operations (except for RRX) as if they used the EX1
373 let Latency = 0; // Bypassable out of EX1
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td215 // ALU - ALU input operands are generally needed in EX1. An operand produced in
216 // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
/llvm-project-15.0.7/llvm/unittests/IR/
H A DPatternMatch.cpp948 Value *EX1 = IRB.CreateExtractElement(VI4, Val); in TEST_F() local
987 EXPECT_TRUE(match(EX1, m_ExtractElt(m_Value(A), m_Value(B)))); in TEST_F()
991 EXPECT_FALSE(match(EX1, m_ExtractElt(m_Value(), m_ConstantInt()))); in TEST_F()