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Searched refs:ENDLOOP (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/
H A Dnested-loop-order.ll24 br i1 %tmp22, label %ENDLOOP, label %ENDIF
27 ; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer
29 ; CHECK: ENDLOOP:
31 ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP
51 br i1 %tmp32, label %ENDLOOP, label %LOOP
64 br i1 %tmp36, label %ENDLOOP, label %LOOP.outer
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dregalloc-coal-extend-short-subrange.mir4 # CHECK: ENDLOOP
H A Dbug6757-endloop.ll3 ; Make sure that we can handle loops with multiple ENDLOOP instructions.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsi-annotate-cf.ll22 ; SI-NEXT: ; %bb.2: ; %ENDLOOP
46 ; FLAT-NEXT: ; %bb.2: ; %ENDLOOP
59 ENDLOOP:
64 br i1 %1, label %ENDLOOP, label %ENDIF
H A Dsi-spill-cf.ll86 br i1 %tmp67, label %ENDLOOP, label %ENDIF
88 ENDLOOP: ; preds = %ELSE2566, %LOOP
247 br i1 %tmp201, label %ENDLOOP, label %ELSE2593
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSchedule.td19 // to schedule an ENDLOOP with 4 other instructions.
H A DHexagonHardwareLoops.cpp1142 unsigned ENDLOOP; in convertToHardwareLoop() local
1152 ENDLOOP = Hexagon::ENDLOOP1; in convertToHardwareLoop()
1157 ENDLOOP = Hexagon::ENDLOOP0; in convertToHardwareLoop()
1276 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart); in convertToHardwareLoop()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MachineCFGStructurizer.cpp665 && It->getOpcode() == R600::ENDLOOP) in wrapup()
1404 insertInstrEnd(DstBlk, R600::ENDLOOP, DebugLoc()); in mergeLooplandBlock()
H A DR600ControlFlowFinalizer.cpp550 case R600::ENDLOOP: { in runOnMachineFunction()
H A DR600Instructions.td1631 def ENDLOOP : ILFormat< (outs), (ins),
1632 "ENDLOOP", []>;