| /llvm-project-15.0.7/llvm/lib/ExecutionEngine/Orc/ |
| H A D | SimpleRemoteEPC.cpp | 265 std::promise<MSVCPExpected<SimpleRemoteEPCExecutorInfo>> EIP; in setup() local
266 auto EIF = EIP.get_future(); in setup()
273 EIP.set_value( in setup()
282 EIP.set_value(EI); in setup()
284 EIP.set_value(make_error<StringError>( in setup()
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| /llvm-project-15.0.7/llvm/include/llvm/Support/Solaris/sys/ |
| H A D | regset.h | 32 #undef EIP
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| /llvm-project-15.0.7/llvm/test/DebugInfo/ |
| H A D | dwarfdump-debug-frame-simple.test | 10 ; FRAMES-NEXT: DW_CFA_offset: {{reg8|EIP}} -4
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| /llvm-project-15.0.7/clang-tools-extra/modularize/ |
| H A D | PreprocessorTracker.cpp | 1152 EIP = MacroInfo.InclusionPathHandles.end(); in reportInconsistentMacros() local
1153 IIP != EIP; ++IIP) { in reportInconsistentMacros()
1213 EIP = MacroInfo.InclusionPathHandles.end(); in reportInconsistentConditionals() local
1214 IIP != EIP; ++IIP) { in reportInconsistentConditionals()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
695 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
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| H A D | X86RegisterInfo.td | 151 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
188 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | sjlj-eh.ll | 49 ; UFC.__jbuf[1] = $EIP
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86WinCOFFTargetStreamer.cpp | 304 case X86::EIP: OS << "$eip"; break; in printFPOReg()
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| H A D | X86MCTargetDesc.cpp | 99 if (Base.isReg() && Base.getReg() == X86::EIP) { in is32BitMemOperand()
411 : X86::EIP; // Should have dwarf #8. in createX86MCRegisterInfo()
459 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
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| H A D | X86MCCodeEmitter.cpp | 335 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode in emitMemModRMByte()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 335 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
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| H A D | X86AsmParser.cpp | 1299 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
1319 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) || in CheckBaseRegAndIndexRegAndScale()
1320 IndexReg == X86::EIP || IndexReg == X86::RIP || in CheckBaseRegAndIndexRegAndScale()
1372 (BaseReg == X86::RIP || BaseReg == X86::EIP)) { in CheckBaseRegAndIndexRegAndScale()
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| /llvm-project-15.0.7/llvm/include/llvm/DebugInfo/CodeView/ |
| H A D | CodeViewRegisters.def | 84 CV_REGISTER(EIP, 33)
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| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | index.rst | 68 ECX, EDI, EDX, EFLAGS, EIP, ESI, ESP, FP0, FP1, FP2, FP3, FP4, FP5, FP6, IP,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86Disassembler.cpp | 2095 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP : in translateRMMemory()
|