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Searched refs:DwarfRegNum (Results 1 – 25 of 27) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td129 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
131 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
156 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
157 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
158 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
159 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
228 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
283 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
284 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
285 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td44 def R1 : LoongArchReg<1, "r1", ["ra"]>, DwarfRegNum<[1]>;
45 def R2 : LoongArchReg<2, "r2", ["tp"]>, DwarfRegNum<[2]>;
46 def R3 : LoongArchReg<3, "r3", ["sp"]>, DwarfRegNum<[3]>;
47 def R4 : LoongArchReg<4, "r4", ["a0"]>, DwarfRegNum<[4]>;
48 def R5 : LoongArchReg<5, "r5", ["a1"]>, DwarfRegNum<[5]>;
49 def R6 : LoongArchReg<6, "r6", ["a2"]>, DwarfRegNum<[6]>;
50 def R7 : LoongArchReg<7, "r7", ["a3"]>, DwarfRegNum<[7]>;
51 def R8 : LoongArchReg<8, "r8", ["a4"]>, DwarfRegNum<[8]>;
52 def R9 : LoongArchReg<9, "r9", ["a5"]>, DwarfRegNum<[9]>;
64 def R21 : LoongArchReg<21, "r21", [""]>, DwarfRegNum<[21]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td52 def R0 : CSKYReg<0, "r0", ["a0"]>, DwarfRegNum<[0]>;
53 def R1 : CSKYReg<1, "r1", ["a1"]>, DwarfRegNum<[1]>;
54 def R2 : CSKYReg<2, "r2", ["a2"]>, DwarfRegNum<[2]>;
55 def R3 : CSKYReg<3, "r3", ["a3"]>, DwarfRegNum<[3]>;
56 def R4 : CSKYReg<4, "r4", ["l0"]>, DwarfRegNum<[4]>;
57 def R5 : CSKYReg<5, "r5", ["l1"]>, DwarfRegNum<[5]>;
58 def R6 : CSKYReg<6, "r6", ["l2"]>, DwarfRegNum<[6]>;
59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
60 def R8 : CSKYReg<8, "r8", ["l4"]>, DwarfRegNum<[8]>;
61 def R9 : CSKYReg<9, "r9", ["l5"]>, DwarfRegNum<[9]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td36 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
37 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
38 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
39 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
40 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
41 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
42 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
43 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
44 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
45 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td129 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
130 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
131 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
132 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
133 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
134 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
135 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
136 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
137 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
138 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
172 DwarfRegNum<[!add(I, 32)]>;
178 DwarfRegNum<[!add(I, 32)]>;
181 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
182 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
183 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
184 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
185 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
186 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
187 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td80 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
82 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
83 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
84 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
85 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
86 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
87 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
88 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
91 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
217 DwarfRegNum<[!add(Index, 32)]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td192 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
193 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
194 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
195 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
196 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
197 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
198 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
199 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
212 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
213 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td31 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
35 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
39 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
44 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
46 def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
47 def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;
48 def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>;
49 def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;
50 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
51 def BLINK : Core<31, "%blink">, DwarfRegNum<[31]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td36 def SPEACC: DwarfRegNum<[99, 111]>;
39 def ACC0 : ACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;
40 def ACC1 : ACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[-1, -1]>;
41 def ACC2 : ACC<2, "acc2", [VSRp4, VSRp5]>, DwarfRegNum<[-1, -1]>;
42 def ACC3 : ACC<3, "acc3", [VSRp6, VSRp7]>, DwarfRegNum<[-1, -1]>;
43 def ACC4 : ACC<4, "acc4", [VSRp8, VSRp9]>, DwarfRegNum<[-1, -1]>;
44 def ACC5 : ACC<5, "acc5", [VSRp10, VSRp11]>, DwarfRegNum<[-1, -1]>;
45 def ACC6 : ACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>;
46 def ACC7 : ACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>;
61 def UACC0 : UACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;
[all …]
H A DPPCRegisterInfo.td124 DwarfRegNum<[Index, -2]>;
170 DwarfRegNum<[-1, -1]>;
178 DwarfRegNum<[-1, -1]>;
246 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
248 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
251 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
252 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
255 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
258 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
260 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td68 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
69 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
70 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
71 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
72 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
73 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
74 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
75 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
76 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
142 def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td79 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
80 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
81 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
82 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
83 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
84 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
85 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
86 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
89 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
90 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td105 def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>;
112 DwarfRegNum<[I]>;
117 def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>;
118 def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>;
119 def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>;
120 def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>;
121 def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>;
122 def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>;
128 ["s"#I]>, DwarfRegNum<[I]>;
145 def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>;
[all …]
/llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp235 uint64_t DwarfRegNum; in prettyPrintRegisterOp() local
240 DwarfRegNum = Operands[OpNum++]; in prettyPrintRegisterOp()
242 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp()
244 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp()
417 uint64_t DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
420 OS << "<unknown register " << DwarfRegNum << ">"; in printCompactDWARFExpr()
428 int DwarfRegNum = Op.getRawOperand(0); in printCompactDWARFExpr() local
432 OS << "<unknown register " << DwarfRegNum << ">"; in printCompactDWARFExpr()
466 uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0; in printCompactDWARFExpr() local
469 OS << "<unknown register " << DwarfRegNum << ">"; in printCompactDWARFExpr()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DStackMaps.cpp249 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand() local
250 unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
256 DwarfRegNum, Offset); in parseOperand()
330 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " in print()
340 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); in createLiveOutReg() local
342 return LiveOutReg(Reg, DwarfRegNum, Size); in createLiveOutReg()
364 return LHS.DwarfRegNum < RHS.DwarfRegNum; in parseRegisterLiveOutMask()
369 if (I->DwarfRegNum != II->DwarfRegNum) { in parseRegisterLiveOutMask()
698 OS.emitInt16(LO.DwarfRegNum); in emitCallsiteEntries()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DStackMaps.h274 unsigned short DwarfRegNum = 0; member
278 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum, in LiveOutReg()
280 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} in LiveOutReg()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td33 def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
35 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td87 DwarfRegNum<[I]>;
228 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
233 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
262 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
336 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;
346 def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp401 for (auto &DwarfRegNum : DwarfRegNums) in EmitRegMappingTables() local
402 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) in EmitRegMappingTables()
403 DwarfRegNum.second.push_back(-1); in EmitRegMappingTables()
422 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
423 int DwarfRegNo = DwarfRegNum.second[I]; in EmitRegMappingTables()
426 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; in EmitRegMappingTables()
483 for (auto &DwarfRegNum : DwarfRegNums) { in EmitRegMappingTables() local
484 int RegNo = DwarfRegNum.second[i]; in EmitRegMappingTables()
488 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td26 def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td181 def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
195 defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
198 def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
307 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
315 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
322 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td19 : Register<N, ALTNAMES>, DwarfRegNum<DWREGS> {
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst366 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
368 This defines the register ``AL`` and assigns it values (with ``DwarfRegNum``)
370 register. For register ``AL``, ``DwarfRegNum`` takes an array of 3 values
457 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
458 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
460 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
461 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
463 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
464 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;

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