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Searched refs:DstVec (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp443 Register DstVec = DstIsLeft ? Left : Right; in matchINS() local
452 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
462 Register DstVec, SrcVec; in applyINS() local
464 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
468 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst); in applyINS()
H A DAArch64InstructionSelector.cpp5511 Register DstVec = ScalarToVec->getOperand(0).getReg(); in selectBuildVector() local
5520 PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB, in selectBuildVector()
5522 DstVec = PrevMI->getOperand(0).getReg(); in selectBuildVector()
5530 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
5550 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
/llvm-project-15.0.7/llvm/lib/IR/
H A DVerifier.cpp2979 bool DstVec = DestTy->isVectorTy(); in visitUIToFPInst() local
2981 Check(SrcVec == DstVec, in visitUIToFPInst()
2988 if (SrcVec && DstVec) in visitUIToFPInst()
3002 bool DstVec = DestTy->isVectorTy(); in visitSIToFPInst() local
3004 Check(SrcVec == DstVec, in visitSIToFPInst()
3011 if (SrcVec && DstVec) in visitSIToFPInst()
3025 bool DstVec = DestTy->isVectorTy(); in visitFPToUIInst() local
3027 Check(SrcVec == DstVec, in visitFPToUIInst()
3033 if (SrcVec && DstVec) in visitFPToUIInst()
3049 Check(SrcVec == DstVec, in visitFPToSIInst()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9966 SDValue DstVec; in LowerBUILD_VECTORvXi1() local
9973 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH); in LowerBUILD_VECTORvXi1()
9978 DstVec = DAG.getBitcast(VecVT, Imm); in LowerBUILD_VECTORvXi1()
9979 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
9983 DstVec = DAG.getUNDEF(VT); in LowerBUILD_VECTORvXi1()
9987 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
9991 return DstVec; in LowerBUILD_VECTORvXi1()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10575 SDValue DstVec = DstIsLeft ? V1 : V2; in LowerVECTOR_SHUFFLE() local
10592 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()