Searched refs:DstRegBank (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
927 assert(DstRegBank.getID() == ARM::GPRRegBankID && in select()
947 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
1017 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 238 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy() local
248 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
281 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
284 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 890 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy() local
903 if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1)) in getRegClassesForCopy()
907 getMinClassForRegBank(DstRegBank, DstSize, true)}; in getRegClassesForCopy()
915 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy() local
945 getMinClassForRegBank(DstRegBank, SrcSize, /* GetAllRegSet */ true); in selectCopy()
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