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Searched refs:Dst0Reg (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1826 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc() local
1827 LLT Dst0Ty = MRI.getType(Dst0Reg); in applyCombineUnmergeWithDeadLanesToTrunc()
1830 Builder.buildCast(Dst0Reg, MIB); in applyCombineUnmergeWithDeadLanesToTrunc()
1832 Builder.buildTrunc(Dst0Reg, SrcReg); in applyCombineUnmergeWithDeadLanesToTrunc()
1839 Register Dst0Reg = MI.getOperand(0).getReg(); in matchCombineUnmergeZExtToZExt() local
1840 LLT Dst0Ty = MRI.getType(Dst0Reg); in matchCombineUnmergeZExtToZExt()
1866 Register Dst0Reg = MI.getOperand(0).getReg(); in applyCombineUnmergeZExtToZExt() local
1874 LLT Dst0Ty = MRI.getType(Dst0Reg); in applyCombineUnmergeZExtToZExt()
1880 Builder.buildZExt(Dst0Reg, ZExtSrcReg); in applyCombineUnmergeZExtToZExt()
1884 replaceRegWith(MRI, Dst0Reg, ZExtSrcReg); in applyCombineUnmergeZExtToZExt()
H A DLegalizerHelper.cpp1629 Register Dst0Reg = MI.getOperand(0).getReg(); in widenScalarUnmergeValues() local
1630 LLT DstTy = MRI.getType(Dst0Reg); in widenScalarUnmergeValues()
1659 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); in widenScalarUnmergeValues()
6528 Register Dst0Reg = MI.getOperand(0).getReg(); in lowerUnmergeValues() local
6529 LLT DstTy = MRI.getType(Dst0Reg); in lowerUnmergeValues()
6540 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); in lowerUnmergeValues()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp410 Register Dst0Reg = I.getOperand(0).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
438 BuildMI(*BB, &I, DL, TII.get(HasCarryIn ? CarryOpc : NoCarryOpc), Dst0Reg) in selectG_UADDO_USUBO_UADDE_USUBE()
447 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()