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Searched refs:DppCtrl (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp908 } else if (Imm <= DppCtrl::QUAD_PERM_LAST) { in printDPPCtrl()
915 (Imm <= DppCtrl::ROW_SHL_LAST)) { in printDPPCtrl()
919 (Imm <= DppCtrl::ROW_SHR_LAST)) { in printDPPCtrl()
923 (Imm <= DppCtrl::ROW_ROR_LAST)) { in printDPPCtrl()
926 } else if (Imm == DppCtrl::WAVE_SHL1) { in printDPPCtrl()
932 } else if (Imm == DppCtrl::WAVE_ROL1) { in printDPPCtrl()
938 } else if (Imm == DppCtrl::WAVE_SHR1) { in printDPPCtrl()
944 } else if (Imm == DppCtrl::WAVE_ROR1) { in printDPPCtrl()
950 } else if (Imm == DppCtrl::ROW_MIRROR) { in printDPPCtrl()
954 } else if (Imm == DppCtrl::BCAST15) { in printDPPCtrl()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp507 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov() local
508 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov()
509 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) { in combineDPPMov()
H A DSIInstrInfo.cpp4543 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || in verifyInstruction()
4544 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || in verifyInstruction()
4545 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || in verifyInstruction()
4546 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || in verifyInstruction()
4547 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || in verifyInstruction()
4548 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || in verifyInstruction()
4549 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { in verifyInstruction()
4553 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && in verifyInstruction()
4559 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && in verifyInstruction()
4565 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST && in verifyInstruction()
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H A DSIDefines.h801 enum DppCtrl : unsigned { enum
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp8477 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || in isDPPCtrl()
8478 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || in isDPPCtrl()
8479 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || in isDPPCtrl()
8480 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || in isDPPCtrl()
8487 (Imm == DppCtrl::BCAST15) || in isDPPCtrl()
8488 (Imm == DppCtrl::BCAST31) || in isDPPCtrl()
8489 (Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) || in isDPPCtrl()
8490 (Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST); in isDPPCtrl()
8703 Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31; in parseDPPCtrlSel()
8732 Val = DppCtrl::ROW_MIRROR; in parseDPPCtrl()
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