Searched refs:DivScale1 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4001 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local
4008 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64()
4009 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64()
4021 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64()
4029 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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| H A D | SIISelLowering.cpp | 9126 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local
9129 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
9132 NegDivScale0, Mul, DivScale1); in LowerFDIV64()
9146 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
9160 Scale = DivScale1.getValue(1); in LowerFDIV64()
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