Searched refs:DivRemResultReg (Results 1 – 2 of 2) sorted by relevance
1522 unsigned DivRemResultReg; // Register containing the desired result. in selectDivRem() member1647 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()1669 .addReg(OpEntry.DivRemResultReg); in selectDivRem()
1889 unsigned DivRemResultReg; // Register containing the desired result. in X86SelectDivRem() member2001 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2019 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()