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Searched refs:DispatchWidth (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp34 if (!DispatchWidth) in DispatchStage()
35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
82 if (NumMicroOps > DispatchWidth) { in dispatch()
83 assert(AvailableEntries == DispatchWidth); in dispatch()
85 CarryOver = NumMicroOps - DispatchWidth; in dispatch()
130 std::min(DispatchWidth, NumMicroOps)); in dispatch()
138 AvailableEntries = DispatchWidth; in cycleStart()
142 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver; in cycleStart()
143 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries; in cycleStart()
161 unsigned Required = std::min(NumMicroOps, DispatchWidth); in isAvailable()
[all …]
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp27 : SM(Model), Source(S), DispatchWidth(Width ? Width : Model.IssueWidth), in SummaryView()
74 TempStream << "\nDispatch Width: " << DV.DispatchWidth; in printView()
91 DV.DispatchWidth = DispatchWidth; in collectData()
95 DV.BlockRThroughput = computeBlockRThroughput(SM, DispatchWidth, NumMicroOps, in collectData()
106 {"DispatchWidth", DV.DispatchWidth}, in toJSON()
H A DSummaryView.h43 const unsigned DispatchWidth; variable
54 unsigned DispatchWidth; member
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DContext.h38 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), in MicroOpQueueSize()
43 unsigned DispatchWidth; member
H A DSupport.h109 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
/llvm-project-15.0.7/llvm/lib/MCA/
H A DSupport.cpp82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput() argument
88 double Max = static_cast<double>(NumMicroOps) / DispatchWidth; in computeBlockRThroughput()
H A DContext.cpp49 std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF); in createDefaultPipeline()
/llvm-project-15.0.7/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp68 if (PO.DispatchWidth) in getJSONSimulationParameters()
69 SimParameters.try_emplace("-dispatch", PO.DispatchWidth); in getJSONSimulationParameters()
H A Dllvm-mca.cpp118 DispatchWidth("dispatch", cl::desc("Override the processor dispatch width"), variable
499 mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth, in main()
636 std::make_unique<mca::SummaryView>(SM, Insts, DispatchWidth)); in main()
/llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/
H A DDispatchStage.h50 unsigned DispatchWidth; variable
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/X86/
H A DTestIncrementalMCA.cpp32 PO.DispatchWidth); in TEST_F()
119 PO.DispatchWidth); in TEST_F()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/
H A DMCATestBase.cpp104 ThePO.DispatchWidth); in runBaselineMCA()
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-mca.rst405 Field *DispatchWidth* is the maximum number of micro opcodes that are dispatched
407 in-order backend, *DispatchWidth* is the maximum number of micro opcodes issued