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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/
H A Dcpus.s28 # BARCELONA: Dispatch Width: 4
33 # BDVER2: Dispatch Width: 4
38 # BROADWELL: Dispatch Width: 4
43 # BTVER2: Dispatch Width: 2
48 # HASWELL: Dispatch Width: 4
53 # ICX: Dispatch Width: 6
58 # IVYBRIDGE: Dispatch Width: 4
63 # KNL: Dispatch Width: 4
68 # SANDYBRIDGE: Dispatch Width: 4
73 # SKX: Dispatch Width: 6
[all …]
H A Duop-queue.s22 # BTVER2-DEC-2: Dispatch Width: 2
67 # BTVER2-DEC-1: Dispatch Width: 2
72 # BTVER2-UOPQ-1: Dispatch Width: 2
77 # BTVER2-UOPQ-2: Dispatch Width: 2
82 # HASWELL-DEC-2: Dispatch Width: 4
87 # HASWELL-UOPQ-1: Dispatch Width: 4
92 # HASWELL-UOPQ-2: Dispatch Width: 4
97 # HASWELL-UOPQ-3: Dispatch Width: 4
102 # HASWELL-UOPQ-4: Dispatch Width: 4
H A Dread-after-ld-1.s50 # BARCELONA: Dispatch Width: 4
55 # BDVER2: Dispatch Width: 4
60 # BDWELL: Dispatch Width: 4
65 # BTVER2: Dispatch Width: 2
70 # HASWELL: Dispatch Width: 4
75 # SANDY: Dispatch Width: 4
80 # SKYLAKE: Dispatch Width: 6
85 # ZNVER1: Dispatch Width: 4
90 # ZNVER2: Dispatch Width: 4
95 # ZNVER3: Dispatch Width: 6
H A Dvariable-blend-read-after-ld-1.s55 # BDVER2: Dispatch Width: 4
60 # BDWELL: Dispatch Width: 4
65 # BTVER2: Dispatch Width: 2
70 # HASWELL: Dispatch Width: 4
75 # IVY: Dispatch Width: 4
80 # SANDY: Dispatch Width: 4
85 # SKYLAKE: Dispatch Width: 6
90 # ZNVER1: Dispatch Width: 4
95 # ZNVER2: Dispatch Width: 4
H A Dvariable-blend-read-after-ld-2.s55 # BDVER2: Dispatch Width: 4
60 # BDWELL: Dispatch Width: 4
65 # BTVER2: Dispatch Width: 2
70 # HASWELL: Dispatch Width: 4
75 # IVY: Dispatch Width: 4
80 # SANDY: Dispatch Width: 4
85 # SKYLAKE: Dispatch Width: 6
90 # ZNVER1: Dispatch Width: 4
95 # ZNVER2: Dispatch Width: 4
H A Dbextr-read-after-ld.s38 # BDVER2: Dispatch Width: 4
43 # BDWELL: Dispatch Width: 4
48 # BTVER2: Dispatch Width: 2
53 # HASWELL: Dispatch Width: 4
58 # SKYLAKE: Dispatch Width: 6
63 # ZNVER1: Dispatch Width: 4
68 # ZNVER2: Dispatch Width: 4
H A Dread-after-ld-3.s17 # BDWELL: Dispatch Width: 4
22 # HASWELL: Dispatch Width: 4
27 # SANDY: Dispatch Width: 4
32 # SKYLAKE: Dispatch Width: 6
H A Dbzhi-read-after-ld.s23 # BDWELL: Dispatch Width: 4
28 # HASWELL: Dispatch Width: 4
33 # SKYLAKE: Dispatch Width: 6
38 # ZNVER1: Dispatch Width: 4
43 # ZNVER2: Dispatch Width: 4
H A Dfma3-read-after-ld-1.s32 # BDWELL: Dispatch Width: 4
37 # HASWELL: Dispatch Width: 4
42 # SKYLAKE: Dispatch Width: 6
47 # ZNVER1: Dispatch Width: 4
H A Dfma3-read-after-ld-2.s32 # BDWELL: Dispatch Width: 4
37 # HASWELL: Dispatch Width: 4
42 # SKYLAKE: Dispatch Width: 6
47 # ZNVER1: Dispatch Width: 4
H A Doption-all-stats-1.s14 # ALL: Dispatch Width: 2
30 # FULLREPORT: Dynamic Dispatch Stall Cycles:
39 # FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
/llvm-project-15.0.7/lldb/source/Plugins/ScriptInterpreter/Python/
H A DScriptedProcessPythonInterface.cpp65 StructuredData::ObjectSP obj = Dispatch("is_alive", error); in ShouldStop()
80 auto mem_region = Dispatch<llvm::Optional<MemoryRegionInfo>>( in GetMemoryRegionContainingAddress()
94 Dispatch<StructuredData::DictionarySP>("get_threads_info", error); in GetThreadsInfo()
105 StructuredData::ObjectSP obj = Dispatch("get_thread_with_id", error, tid); in GetThreadWithID()
123 return Dispatch<lldb::DataExtractorSP>("read_memory_at_address", error, in ReadMemoryAtAddress()
130 Dispatch<StructuredData::ArraySP>("get_loaded_images", error); in GetLoadedImages()
146 StructuredData::ObjectSP obj = Dispatch("get_process_id", error); in GetProcessID()
156 StructuredData::ObjectSP obj = Dispatch("is_alive", error); in IsAlive()
167 StructuredData::ObjectSP obj = Dispatch("get_scripted_thread_plugin", error); in GetScriptedThreadPluginName()
H A DScriptedThreadPythonInterface.cpp65 StructuredData::ObjectSP obj = Dispatch("get_thread_id", error); in GetThreadID()
75 StructuredData::ObjectSP obj = Dispatch("get_name", error); in GetName()
85 StructuredData::ObjectSP obj = Dispatch("get_state", error); in GetState()
95 StructuredData::ObjectSP obj = Dispatch("get_queue", error); in GetQueue()
106 Dispatch<StructuredData::DictionarySP>("get_stop_reason", error); in GetStopReason()
117 Dispatch<StructuredData::ArraySP>("get_stackframes", error); in GetStackFrames()
128 Dispatch<StructuredData::DictionarySP>("get_register_info", error); in GetRegisterInfo()
139 StructuredData::ObjectSP obj = Dispatch("get_register_context", error); in GetRegisterContext()
/llvm-project-15.0.7/lldb/source/Symbol/
H A DPostfixExpression.cpp114 using Visitor<bool>::Dispatch;
118 return Dispatch(binary.Left()) && Dispatch(binary.Right()); in Visit()
129 return Dispatch(ref); in Visit()
136 return Dispatch(unary.Operand()); in Visit()
146 using Visitor<>::Dispatch;
181 Dispatch(binary.Left()); in Visit()
182 Dispatch(binary.Right()); in Visit()
231 Dispatch(unary.Operand()); in Visit()
243 return SymbolResolver(replacer).Dispatch(node); in ResolveSymbols()
248 DWARFCodegen(stream).Dispatch(ptr); in ToDWARF()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixIrreducibleControlFlow.cpp359 MachineBasicBlock *Dispatch = MF.CreateMachineBasicBlock(); in makeSingleEntryLoop() local
360 MF.insert(MF.end(), Dispatch); in makeSingleEntryLoop()
361 Blocks.insert(Dispatch); in makeSingleEntryLoop()
366 BuildMI(Dispatch, DebugLoc(), TII.get(WebAssembly::BR_TABLE_I32)); in makeSingleEntryLoop()
385 Dispatch->addSuccessor(Entry); in makeSingleEntryLoop()
395 if (Pred != Dispatch) { in makeSingleEntryLoop()
455 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::BR)).addMBB(Dispatch); in makeSingleEntryLoop()
456 Routing->addSuccessor(Dispatch); in makeSingleEntryLoop()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dscheduler-queue-usage.s13 # M3: Dispatch Width: 6
18 # M4: Dispatch Width: 6
23 # M5: Dispatch Width: 6
H A Ddirect-branch.s17 # M3: Dispatch Width: 6
22 # M4: Dispatch Width: 6
27 # M5: Dispatch Width: 6
/llvm-project-15.0.7/lldb/unittests/Symbol/
H A DPostfixExpressionTest.cpp47 Dispatch(binary.Left()), Dispatch(binary.Right()))); in Visit()
66 Dispatch(unary.Operand()))); in Visit()
72 return ASTPrinter().Dispatch(node); in Print()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Dstore-throughput.s60 # CHECK: Dispatch Width: 4
79 # CHECK: Dynamic Dispatch Stall Cycles:
88 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
290 # CHECK: Dispatch Width: 4
309 # CHECK: Dynamic Dispatch Stall Cycles:
318 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
520 # CHECK: Dispatch Width: 4
539 # CHECK: Dynamic Dispatch Stall Cycles:
548 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
752 # CHECK: Dispatch Width: 4
[all …]
H A Dload-throughput.s60 # CHECK: Dispatch Width: 4
79 # CHECK: Dynamic Dispatch Stall Cycles:
88 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
290 # CHECK: Dispatch Width: 4
309 # CHECK: Dynamic Dispatch Stall Cycles:
318 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
520 # CHECK: Dispatch Width: 4
539 # CHECK: Dynamic Dispatch Stall Cycles:
548 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
752 # CHECK: Dispatch Width: 4
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-all-stats.s16 # CHECK: Dispatch Width: 2
37 # CHECK: Dynamic Dispatch Stall Cycles:
46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
H A DA55-all-views.s16 # CHECK: Dispatch Width: 2
37 # CHECK: Dynamic Dispatch Stall Cycles:
46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
H A DA55-out-of-order-retire.s16 # CHECK: Dispatch Width: 2
37 # CHECK: Dynamic Dispatch Stall Cycles:
46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
H A DA55-in-order-retire.s16 # CHECK: Dispatch Width: 2
37 # CHECK: Dynamic Dispatch Stall Cycles:
46 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Dload-store-throughput.s53 # CHECK: Dispatch Width: 4
72 # CHECK: Dynamic Dispatch Stall Cycles:
81 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
247 # CHECK: Dispatch Width: 4
266 # CHECK: Dynamic Dispatch Stall Cycles:
275 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
441 # CHECK: Dispatch Width: 4
460 # CHECK: Dynamic Dispatch Stall Cycles:
469 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:

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