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Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1849 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local
1860 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1874 .addReg(DestSub1) in computeBase()
H A DSIInstrInfo.cpp6738 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
6739 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
6742 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
6748 .addReg(DestSub1) in splitScalar64BitUnaryOp()
6774 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitAddSub() local
6811 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
6821 .addReg(DestSub1) in splitScalar64BitAddSub()
6878 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
6879 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
6887 .addReg(DestSub1) in splitScalar64BitBinaryOp()
H A DSIISelLowering.cpp4010 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
4027 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1); in EmitInstrWithCustomInserter()
4031 .addReg(DestSub1) in EmitInstrWithCustomInserter()
4063 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
4099 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
4109 .addReg(DestSub1) in EmitInstrWithCustomInserter()