Searched refs:Def1 (Results 1 – 8 of 8) sorted by relevance
| /llvm-project-15.0.7/clang/test/SemaTemplate/ |
| H A D | instantiation-default-1.cpp | 2 template<typename T, typename U = const T> struct Def1;
4 template<> struct Def1<int> { struct
8 template<> struct Def1<const int> { // expected-note{{previous definition is here}} struct
12 template<> struct Def1<int&> { struct
16 void test_Def1(Def1<int, const int> *d1, Def1<const int, const int> *d2, in test_Def1()
17 Def1<int&, int&> *d3) { in test_Def1()
39 template<> struct Def1<const int> { }; // expected-error{{redefinition of 'Def1<const int>'}} struct
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 87 MachineInstr *Def1 = nullptr; in processReg() local
165 if (Def1) in processReg()
167 Def1 = &I; in processReg()
188 if (!Def0 || !Def1 || Def0->getParent() != Def1->getParent()) in processReg()
191 LLVM_DEBUG(dbgs() << "Combining:\n " << *Def0 << " " << *Def1 in processReg()
194 if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1), in processReg()
196 std::swap(Def0, Def1); in processReg()
199 LIS->RemoveMachineInstrFromMaps(*Def1); in processReg()
205 Def1->eraseFromParent(); in processReg()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 110 MachineInstr *Def1, *Def2; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
300 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
301 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock()
323 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1; in genMuxInBlock()
324 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
334 if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent()) in genMuxInBlock()
344 B.remove(MX.Def1); in genMuxInBlock()
|
| H A D | HexagonEarlyIfConv.cpp | 480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); in computePhiCost() local
482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) in computePhiCost()
|
| /llvm-project-15.0.7/clang/test/Modules/Inputs/merge-class-definition-visibility/ |
| H A D | modmap | 1 module Def1 {
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 472 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), in createCRLogicalOpInfo() local
474 assert(Def1 && "Must be able to find a definition of operand 1."); in createCRLogicalOpInfo()
476 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg()); in createCRLogicalOpInfo()
489 Ret.TrueDefs = std::make_pair(Def1, Def2); in createCRLogicalOpInfo()
491 Ret.TrueDefs = std::make_pair(Def1, nullptr); in createCRLogicalOpInfo()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1915 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
1918 if (!produceSameValue(*Def0, *Def1, MRI)) in produceSameValue()
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5405 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
5407 if (Def1 || Def2) { in buildVector()
5408 SDValue Elem1 = Elems[Def1 ? I1 : I2]; in buildVector()
|