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/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-primary-bases.cpp220 struct DX : virtual B1X { int a; DX() : a(0xf000000D) {} virtual void f() { printf("D"); } }; in DX() struct
291 sizeof(DX)+
H A Dms-x86-aligned-tail-padding.cpp446 struct __declspec(align(16)) DX { struct
448 DX() : a(0xf000000D) {} in DX() argument
476 sizeof(DX)];
H A Dms-x86-lazy-empty-nonvirtual-base.cpp633 struct DX : B8X, B1X, virtual B0X { struct
635 DX() : a(0x0000000D) { printf(" D = %p\n", this); } in DX() argument
733 sizeof(DX)+
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax.s451 shld DX, BX
452 shld DX, BX, CL
453 shld DX, BX, 1
456 shrd DX, BX
458 shrd DX, BX, 1
512 inb DX
513 inw DX
514 inl DX
515 outb DX
516 outw DX
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td268 // A DX pipeline may take 5 cycles to complete.
358 // Save 1 cycles if pipeline BF reads the data from pipelines DX, MU, vMU, CY, DF, MM.
365 // Save 1 cycles if pipeline CY reads the data from pipelines DX, MU, vMU, BF, DF, MM.
372 // Save 1 cycles if pipeline MM reads the data from pipelines DX, MU, vMU, BF, CY, DF.
382 // Save 1 cycles if pipeline DF reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
385 // Save 1 cycles if pipeline DV reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
388 // Save 1 cycles if pipeline DX reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
400 // Save 1 cycles if pipeline MU reads the data from pipelines DX, MU, DF.
412 // Save 1 cycles if pipeline vMU reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dforeach.td11 // CHECK: def DX {
47 def DX : X<[0, 1, 2]>;
H A Dlistconcat.td20 // CHECK: def DX {
46 def DX : X<[0], [1], [2]>;
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-cuid-hash.hip20 // RUN: %clang -### -x hip -target x86_64-unknown-linux-gnu -DX=1 \
24 // RUN: %clang -### -x hip -target x86_64-unknown-linux-gnu -DX=2 \
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test106 - 'ROL16ri DX DX i_0x1'
123 - 'DX=0x0'
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td66 // AX,DX = AX*GR16
92 // AX,DX = AX*[mem16]
113 // AX,DX = AX*GR16
131 // AX,DX = AX*[mem16]
286 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
287 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
301 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
302 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
318 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
319 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
[all …]
H A DX86RegisterInfo.td116 def DX : X86Reg<"dx", 2, [DL,DH]>;
144 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
411 (add AX, CX, DX, SI, DI, BX, BP, SP,
458 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
478 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
521 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
H A DX86CallingConv.td49 let GPR_16 = [AX, CX, DX, DI, SI];
69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W];
76 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W];
213 // Scalar values are returned in AX first, then DX. For i8, the ABI
226 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
295 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
408 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,
677 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ],
937 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>,
H A DX86InstrSystem.td82 let Defs = [AL], Uses = [DX] in
84 let Defs = [AX], Uses = [DX] in
87 let Defs = [EAX], Uses = [DX] in
101 let Uses = [DX, AL] in
103 let Uses = [DX, AX] in
106 let Uses = [DX, EAX] in
H A DX86InstrExtension.td26 let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
H A DX86InstructionSelector.cpp1537 X86::DX, in selectDivRem()
1540 {X86::IDIV16r, X86::CWD, Copy, X86::DX, S}, // SRem in selectDivRem()
1542 {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem in selectDivRem()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp189 {codeview::RegisterId::DX, X86::DX}, in initLLVMToSEHAndCVRegMapping()
759 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
771 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
808 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
809 return X86::DX; in getX86SubSuperRegisterOrZero()
844 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
880 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/MachO/
H A Ddylib.test14 RUN: llvm-otool -DX %p/Inputs/dylibLoadKinds.macho-x86_64 | FileCheck %s --check-prefix=IDNOHEADERS
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/misc/
H A Dredundant-expression.cpp94 template <int DX>
96 if (DX > 0 && DX > 0) return 1; in TestSimpleEquivalentDependent()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2010-02-23-RematImplicitSubreg.ll9 ; sub-registers %DX and %EDX.
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp221 unsigned DX = (MO.getImm() >> 3) & 0x3F; in getMemRIHashEncoding() local
222 return RegBits | DX; in getMemRIHashEncoding()
/llvm-project-15.0.7/mlir/test/Conversion/TosaToLinalg/
H A Dtosa-to-linalg.mlir1646 // CHECK: %[[DX:.+]] = arith.subf %[[VAL9:.+]], %[[VAL11]]
1694 // CHECK: %[[NDX:.+]] = arith.subf %[[ONE]], %[[DX]]
1696 // CHECK: %[[WLOHI:.+]] = arith.mulf %[[LOHI]], %[[DX]]
1699 // CHECK: %[[WHIHI:.+]] = arith.mulf %[[HIHI]], %[[DX]]
1797 // CHECK: %[[DX:.+]] = arith.subi %11, %[[ROUNDX]]
1847 // CHECK: %[[NDX:.+]] = arith.subi %[[SCALE]], %[[DX]]
1849 // CHECK: %[[WLOHI:.+]] = arith.muli %[[XLOHI]], %[[DX]]
1852 // CHECK: %[[WHIHI:.+]] = arith.muli %[[XHIHI]], %[[DX]]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td70 def DX : ExtInfo_rr<DExt, FPR64, GPR>;
84 defvar DXINX = [DX, DX_INX, DX_IN32X];
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h118 ENTRY(DX) \
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DSnippetGeneratorTest.cpp359 AllRegisters.reset(X86::DX); in TEST_F()
/llvm-project-15.0.7/llvm/test/Transforms/LoopReroll/
H A Dnonconst_lb.ll110 ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[DX:%.*]], i32 [[TMP5]]

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