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/llvm-project-15.0.7/openmp/libomptarget/DeviceRTL/src/
H A DWorkshare.cpp275 DST->LoopUpperBound = ub; in dispatch_init()
281 DST->Chunk = chunk; in dispatch_init()
283 DST->Stride = stride; in dispatch_init()
304 DST->Chunk = chunk; in dispatch_init()
306 DST->Stride = stride; in dispatch_init()
318 DST->Chunk = chunk; in dispatch_init()
320 DST->Stride = stride; in dispatch_init()
326 DST->Chunk = chunk; in dispatch_init()
402 ST chunk = DST->Chunk; in dispatch_next()
411 ST stride = DST->Stride; in dispatch_next()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ConstraintElimination/
H A Dgeps-precondition-overflow-check.ll10 ; CHECK-NEXT: [[DST_5:%.*]] = getelementptr i32, i32* [[DST:%.*]], i64 5
11 ; CHECK-NEXT: [[DST_5_UGE:%.*]] = icmp uge i32* [[DST_5]], [[DST]]
14 ; CHECK-NEXT: [[DST_4:%.*]] = getelementptr i32, i32* [[DST]], i64 4
15 ; CHECK-NEXT: [[TRUE_DST_4_UGE:%.*]] = icmp uge i32* [[DST_4]], [[DST]]
38 ; CHECK-NEXT: [[DST_5_UGE:%.*]] = icmp uge i32* [[DST_5]], [[DST]]
42 ; CHECK-NEXT: [[DST_4:%.*]] = getelementptr i32, i32* [[DST]], i64 4
67 ; CHECK-NEXT: [[DST_5_UGE:%.*]] = icmp uge i32* [[DST_5]], [[DST]]
71 ; CHECK-NEXT: [[DST_4:%.*]] = getelementptr i32, i32* [[DST]], i64 4
72 ; CHECK-NEXT: [[DST_4_UGE:%.*]] = icmp uge i32* [[DST_4]], [[DST]]
100 ; CHECK-NEXT: [[DST_5_UGE:%.*]] = icmp uge i32* [[DST_5]], [[DST]]
[all …]
/llvm-project-15.0.7/libclc/generic/lib/
H A Dgen_convert.py190 """.format(SRC=src, DST=dst, M=mode))
199 """.format(SRC=src, DST=dst, N=size, H=half_size, M=mode))
206 }}""".format(SRC=src, DST=dst, M=mode))
237 {{""".format(DST=dst, SRC=src, N=size))
262 return y;""".format(SRC=src, DST=dst, N=size,
287 print(" return convert_{DST}{N}(x);".format(DST=dst, N=size))
311 """.format(DST=dst, SRC=src, N=size, M=mode))
343 {{""".format(SRC=src, DST=dst, N=size, M=mode, S=sat))
367 .format(DST=dst, N=size, BOOL=bool_type[dst]))
370 .format(DST=dst, N=size, BOOL=bool_type[dst]))
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmempcpy.ll5 ; (2) its return value is DST+N i.e. the dst pointer adjusted by the copy size.
7 ; adjust the dst pointer, DST+N is explicitly computed and stored to a global
8 ; variable G before the mempcpy call. This instance of DST+N causes the repeat
9 ; DST+N done in the context of the return value of mempcpy to be redundant, and
11 ; (2) to be expressed as verifying that the MOV to store DST+N to G and
12 ; the MOV to copy DST+N to %rax use the same source register.
23 define dso_local ptr @RET_MEMPCPY(ptr %DST, ptr %SRC, i64 %N) {
24 %add.ptr = getelementptr inbounds i8, ptr %DST, i64 %N
26 %call = tail call ptr @mempcpy(ptr %DST, ptr %SRC, i64 %N)
H A Dmempcpy-32.ll13 define ptr @RET_MEMPCPY(ptr %DST, ptr %SRC, i32 %N) {
14 %add.ptr = getelementptr inbounds i8, ptr %DST, i32 %N
16 %call = tail call ptr @mempcpy(ptr %DST, ptr %SRC, i32 %N)
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Dmemory-intrinsics-sizes.ll97 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC]], i64 100, i1 false)
107 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DST:%.*]], i8* [[SRC:%.*]], i64 100, i1…
140 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC:%.*]], i64 100, i1 fal…
150 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[DST:%.*]], i8 0, i64 100, i1 false)
172 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[DST]], i8 0, i64 [[LEN_2:%.*]], i1 f…
183 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[DST]], i8 0, i64 100, i1 false)
194 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[DST]], i8 0, i64 [[LEN_1:%.*]], i1 f…
226 ; CHECK-NEXT: call void @llvm.memmove.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC]], i64 100, i1 false)
269 ; CHECK-NEXT: call void @llvm.memmove.p0i8.p0i8.i64(i8* [[DST]], i8* [[SRC:%.*]], i64 100, i1 fa…
279 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[DST:%.*]], i8 0, i64 100, i1 false)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr30451.ll13 ; CHECK: lbarx [[DST:[0-9]+]],
14 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
29 ; CHECK: lharx [[DST:[0-9]+]],
30 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
46 ; CHECK: lbarx [[DST:[0-9]+]],
47 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
62 ; CHECK: lharx [[DST:[0-9]+]],
63 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsprintf-1.ll39 ; CHECK-NEXT: store i8 0, i8* [[DST:%.*]], align 1
49 ; CHECK-NEXT: store i8 0, i8* [[DST:%.*]], align 1
61 ; CHECK-NEXT: store i8 104, i8* [[DST:%.*]], align 1
62 ; CHECK-NEXT: [[NUL:%.*]] = getelementptr inbounds i8, i8* [[DST]], i32 1
103 ; WITHSTPCPY-NEXT: [[STPCPY:%.*]] = call i8* @stpcpy(i8* [[DST:%.*]], i8* [[STR:%.*]])
105 ; WITHSTPCPY-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[DST]] to i32
136 ; CHECK-IPRINTF-NEXT: [[STPCPY:%.*]] = call i8* @stpcpy(i8* [[DST:%.*]], i8* [[STR:%.*]])
138 ; CHECK-IPRINTF-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[DST]] to i32
145 ; WIN-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 [[DST:%.*]], i8* align 1 [[STR]], i…
174 ; CHECK-IPRINTF-NEXT: [[STPCPY:%.*]] = call i8* @stpcpy(i8* [[DST:%.*]], i8* [[STR:%.*]])
[all …]
H A Dmemccpy.ll13 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i64*
15 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 8
24 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i64*
26 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 8
127 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 12
137 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 11
147 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 11
157 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, i8* [[DST]], i64 11
183 ; CHECK-NEXT: [[CALL:%.*]] = call i8* @memccpy(i8* [[DST:%.*]], i8* [[SRC:%.*]], i32 114, i64 12)
237 ; CHECK-NEXT: [[CALL:%.*]] = call i8* @memccpy(i8* [[DST:%.*]], i8* getelementptr inbounds ([11 …
[all …]
H A Dstrcpy-nonzero-as.ll16 ; CHECK-SAME: (i8 addrspace(200)* [[DST:%.*]]) addrspace(200) #[[ATTR1:[0-9]+]] {
18 …p200i8.p200i8.i64(i8 addrspace(200)* noundef align 1 dereferenceable(17) [[DST]], i8 addrspace(200…
28 ; CHECK-SAME: (i8 addrspace(200)* [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
30 …p200i8.p200i8.i64(i8 addrspace(200)* noundef align 1 dereferenceable(17) [[DST]], i8 addrspace(200…
40 ; CHECK-SAME: (i8 addrspace(200)* [[DST:%.*]], i8 addrspace(200)* [[SRC:%.*]]) addrspace(200) #[[AT…
42 …all addrspace(200) i8 addrspace(200)* @strcpy(i8 addrspace(200)* noundef [[DST]], i8 addrspace(200…
53 ; CHECK-SAME: (i8 addrspace(200)* [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
55 …200i8.p200i8.i128(i8 addrspace(200)* noundef align 1 dereferenceable(17) [[DST]], i8 addrspace(200…
66 ; CHECK-SAME: (i8 addrspace(200)* [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
68 …*]] = call addrspace(200) i8 addrspace(200)* @stpncpy(i8 addrspace(200)* [[DST]], i8 addrspace(200…
H A Dstrncpy-3.ll14 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i32*
24 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i32*
34 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[DST:%.*]] to i32*
44 …vm.memcpy.p0i8.p0i8.i64(i8* noundef nonnull align 1 dereferenceable(128) [[DST:%.*]], i8* noundef …
53 ; CHECK-NEXT: [[TMP1:%.*]] = tail call i8* @strncpy(i8* noundef nonnull dereferenceable(1) [[DST…
/llvm-project-15.0.7/llvm/test/Transforms/MemCpyOpt/
H A Dnontemporal.ll11 ; CHECK-NEXT: store <4 x float> zeroinitializer, <4 x float>* [[DST:%.*]], align 16, !nontempora…
12 ; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 1
14 ; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 2
16 ; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 3
18 ; CHECK-NEXT: [[PTR4:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 4
20 ; CHECK-NEXT: [[PTR5:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 5
22 ; CHECK-NEXT: [[PTR6:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 6
24 ; CHECK-NEXT: [[PTR7:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 7
50 ; CHECK-NEXT: store <4 x float> zeroinitializer, <4 x float>* [[DST:%.*]], align 16, !nontempora…
51 ; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[DST]], i64 1
H A Dmemset-memcpy-redundant-memset.ll14 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 [[SRC_SIZE]]
109 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 80
124 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 36
139 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 80
151 ; CHECK-NEXT: [[DST:%.*]] = bitcast i64* [[DST_PI64:%.*]] to i8*
228 ; CHECK-NEXT: [[DST:%.*]] = alloca i8, align 1
281 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 16
282 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, i8* [[DST]], i64 16
295 ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i8, i8* [[DST:%.*]], i64 16
296 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, i8* [[DST]], i64 16
[all …]
H A Dfca2memcpy.ll11 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
23 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
35 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
50 ; CHECK-NEXT: store [[S]] [[TMP1]], %S* [[DST:%.*]], align 8
62 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
77 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
80 ; CHECK-NEXT: store [[S]] [[TMP1]], %S* [[DST]], align 8
94 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %S* [[DST:%.*]] to i8*
95 ; CHECK-NEXT: [[DST2:%.*]] = getelementptr [[S:%.*]], %S* [[DST]], i64 1
112 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %S* [[DST:%.*]] to i8*
[all …]
H A Dvariable-sized-memcpy-memcpy.ll8 ; CHECK-NEXT: [[DST:%.*]] = alloca i8, i64 [[SIZE]], align 1
10 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[DST]], i8* align 8 [[SRC]], i64…
25 ; CHECK-NEXT: [[DST:%.*]] = alloca i8, i64 [[SIZE2:%.*]], align 1
27 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[DST]], i8* align 8 [[TMP]], i64…
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dnontrivial-c-struct-within-struct-name.m25 // CHECK: define linkonce_odr hidden void @__destructor_8_S_S_s0(i8** noundef %[[DST:.*]])
27 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
32 // CHECK: define linkonce_odr hidden void @__destructor_8_S_s0(i8** noundef %[[DST:.*]])
34 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
41 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
H A Dweak-in-c-struct.m26 // ARM64: define linkonce_odr hidden void @__default_constructor_8_w8(i8** noundef %[[DST:.*]])
28 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
36 // ARM64: define linkonce_odr hidden void @__destructor_8_w8(i8** noundef %[[DST:.*]])
38 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
57 // ARM64: define linkonce_odr hidden void @__copy_constructor_8_8_t0w4_w8(i8** noundef %[[DST:.*]],…
60 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
83 // ARM64: define linkonce_odr hidden void @__copy_assignment_8_8_t0w4_w8(i8** noundef %[[DST:.*]], …
86 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
114 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8
138 // ARM64: define linkonce_odr hidden void @__move_assignment_8_8_t0w4_w8(i8** noundef %[[DST:.*]], …
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlower-mem-intrinsics-threshold.ll12 ; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
16 ; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
20 ; OPT0-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 0…
27 ; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TM…
41 ; OPT8-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4…
45 ; OPT4-NEXT: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* [[DST:%.*]], i8 [[VAL:%.*]], i64 4…
52 ; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
64 ; OPT_NEG-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TM…
85 ; OPT4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
97 ; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8 addrspace(1)* [[DST:%.*]], i64 [[TMP1]]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dsopc-err.s21 s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
24 s_set_gpr_idx_on s0, gpr_idx(DST
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dvect_copyable_in_binops.ll10 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[DST:%.*]] to <4 x i32>*
42 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[DST]], align 4
83 ; CHECK-NEXT: store i32 [[SUB]], i32* [[DST]], align 4
187 ; CHECK-NEXT: store i32 [[SUB]], i32* [[DST]], align 4
232 ; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[DST]] to <2 x i32>*
310 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[DST]], align 4
414 ; CHECK-NEXT: store float [[TMP0]], float* [[DST]], align 4
455 ; CHECK-NEXT: store float [[ADD]], float* [[DST]], align 4
559 ; CHECK-NEXT: store float [[SUB]], float* [[DST]], align 4
714 ; CHECK-NEXT: store float [[TMP0]], float* [[DST]], align 4
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dpointer-select-runtime-checks.ll19 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP1]]
35 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i8 [[INDUCTION]]
51 ; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i8 [[IV]]
81 ; CHECK-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST:%.*]] to i64
135 ; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i8 [[IV]]
182 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP1_FR]]
185 ; CHECK-NEXT: [[BOUND03:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP2_FR]]
267 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP1]]
270 ; CHECK-NEXT: [[BOUND03:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP2_FR]]
352 ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[UGLYGEP1_FR]]
[all …]
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx8_imask.rst45 * "DST" - enable *dst* indexing.
62 s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
63 s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
65 s_set_gpr_idx_mode gpr_idx(DST,SRC1)
H A Dgfx90a_imask.rst45 * "DST" - enable *dst* indexing.
62 s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
63 s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
65 s_set_gpr_idx_mode gpr_idx(DST,SRC1)
H A Dgfx9_imask.rst45 * "DST" - enable *dst* indexing.
62 s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
63 s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
65 s_set_gpr_idx_mode gpr_idx(DST,SRC1)
H A Dgfx940_imask.rst45 * "DST" - enable *dst* indexing.
62 s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
63 s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
65 s_set_gpr_idx_mode gpr_idx(DST,SRC1)

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