| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
438 .addReg(DReg, 0, Lane); in createExtractSubreg()
476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
482 .addReg(DReg) in createInsertSubreg()
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| H A D | ARMBaseInstrInfo.cpp | 5058 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
5059 return DReg; in getCorrespondingDRegAndLane()
5065 return DReg; in getCorrespondingDRegAndLane()
5088 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
5094 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
5112 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
5163 .addReg(DReg, RegState::Undef) in setExecutionDomain()
5192 MIB.addReg(DReg, RegState::Define) in setExecutionDomain()
5193 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI))) in setExecutionDomain()
5368 if (!DReg || !MI.definesRegister(DReg, TRI)) in getPartialRegUpdateClearance()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 78 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
80 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 935 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
936 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs()
938 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
939 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
941 Defs &= ~(1 << DReg); in adjustLiveRegs()
967 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
968 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs()
970 pushReg(DReg); in adjustLiveRegs()
971 Defs &= ~(1 << DReg); in adjustLiveRegs()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kBaseInfo.h | 61 DReg = 0x8, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4860 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4863 unsigned TmpReg = DReg; in expandRotation()
4869 if (DReg == SReg) { in expandRotation()
4910 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4923 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4973 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm()
4985 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local
4988 unsigned TmpReg = DReg; in expandDRotation()
5035 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation()
5048 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 482 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
489 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 939 unsigned DReg = CSKY::F0_64 + RegNo; in getRegForInlineAsmConstraint() local
942 return std::make_pair(DReg, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint()
944 return std::make_pair(DReg, &CSKY::FPR64RegClass); in getRegForInlineAsmConstraint()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.td | 183 def MxDRegClass : MxOpClass<"DReg">;
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11911 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local
11912 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
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