Home
last modified time | relevance | path

Searched refs:DRC (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCondMov.td20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
72 DRC:$T, DRC:$F),
75 DRC:$T, DRC:$F),
84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
[all …]
H A DMipsInstrFPU.td216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
H A DMipsInstrInfo.td1808 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1809 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1810 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1827 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1828 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1829 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp633 EXPECT_FALSE(DRC.isChildOf(ARC)); in TEST()
637 EXPECT_TRUE(DRC.isChildOf(BRC)); in TEST()
639 EXPECT_TRUE(DRC.isChildOf(CRC)); in TEST()
652 EXPECT_TRUE(ARC.isParentOf(DRC)); in TEST()
656 EXPECT_TRUE(DRC.isChildOf(ARC)); in TEST()
673 EXPECT_TRUE(ARC.isParentOf(DRC)); in TEST()
677 EXPECT_TRUE(DRC.isChildOf(ARC)); in TEST()
694 EXPECT_TRUE(ARC.isParentOf(DRC)); in TEST()
698 EXPECT_TRUE(DRC.isChildOf(ARC)); in TEST()
807 EXPECT_EQ(&DRC, MergedRCs[0]); in TEST()
[all …]
/llvm-project-15.0.7/openmp/libomptarget/include/
H A Ddevice.h62 StatesTy(uint64_t DRC, uint64_t HRC) in StatesTy()
63 : DynRefCount(DRC), HoldRefCount(HRC), in StatesTy()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
781 switch (DRC->getID()) { in buildMux()
802 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
H A DHexagonBitSimplify.cpp961 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
962 if (!DRC) in isTransparentCopy()
965 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1511 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1512 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1519 BT.put(ImmReg, DRC); in processBlock()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td1435 class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1436 : Pseudo<(outs DRC
1440 "atomic_op", [(set DRC
1444 class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1447 : $rd, DRC
1450 : $rd, DRC
1453 class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1454 : Pseudo<(outs DRC:$rd),
1455 (ins PTRRC:$rr, DRC:$operand),
1456 "atomic_op", [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineVerifier.cpp2026 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2028 if (!DRC->contains(Reg)) { in visitMachineOperand()
2031 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2140 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2149 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2150 if (!DRC) { in visitMachineOperand()
2155 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2157 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
H A DMachineSink.cpp283 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
284 if (SRC != DRC) in INITIALIZE_PASS_DEPENDENCY()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp4946 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
4948 return DRC->contains(Reg); in isLegalRegOperand()
4958 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
4959 if (!DRC) in isLegalRegOperand()
4962 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()