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Searched refs:DPP8 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX1011.rst46 DPP8 section in Instructions
H A DAMDGPUAsmGFX10.rst141 DPP8 section in Instructions
H A DAMDGPUAsmGFX1030.rst144 DPP8 section in Instructions
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_dpp.s6 ; DPP8
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td448 // DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
452 "Support DPP8 (Data Parallel Primitives) extension"
H A DVOP2Instructions.td1390 let DecoderNamespace = "DPP8";
1439 let DecoderNamespace = "DPP8";
1523 let DecoderNamespace = "DPP8";
H A DVOPInstructions.td692 // Common refers to common between DPP and DPP8
1505 def VOPC64DPP8Table : VOPC64Table<"DPP8">;
H A DSIInstrInfo.td1269 def dpp8 : NamedOperandU32<"DPP8", NamedMatchClass<"DPP8", 0>>;
2542 // DPP8 encoding has no fields for modifiers, and it is enforced by setting
H A DVOP1Instructions.td772 let DecoderNamespace = "DPP8";
H A DVOPCInstructions.td718 // DPP8 forbids modifiers and can inherit from VOPC_Profile
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp8606 unsigned DPP8 = 0; in parseDPP8() local
8608 DPP8 |= (Sels[i] << (i * 3)); in parseDPP8()
8610 Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8)); in parseDPP8()
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst1106 DPP8 Modifiers