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Searched refs:DPP (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddpp_combine.mir5 # bound_ctrl:1 is set, otherwise the result of DPP VALU op can be undefined.
60 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
73 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
74 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
76 # The VALU op should have the same masks as DPP mov as they select lanes
78 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
83 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
86 # The VALU op should have the same masks as DPP mov as they select
143 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
181 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
[all …]
H A Dvopc_dpp.mir95 ; All cases are covered by generic rules for creating DPP instructions
H A Ddpp_combine_gfx11.mir103 # when the DPP source isn't a src0 operand the operation should be commuted if possible
440 # Test instruction which does not have modifiers in VOP1 form but does in DPP form.
452 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
H A Dllc-pipeline.ll303 ; GCN-O1-NEXT: GCN DPP Combine
585 ; GCN-O1-OPTS-NEXT: GCN DPP Combine
876 ; GCN-O2-NEXT: GCN DPP Combine
1181 ; GCN-O3-NEXT: GCN DPP Combine
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp299 {Identity, V, B.getInt32(DPP::ROW_XMASK0 | 1 << Idx), in buildReduction()
342 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx), in buildScan()
350 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa), in buildScan()
355 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc), in buildScan()
370 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
379 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
398 {Identity, V, B.getInt32(DPP::WAVE_SHR1), B.getInt32(0xf), in buildShiftRight()
410 {Identity, V, B.getInt32(DPP::ROW_SHR0 + 1), in buildShiftRight()
H A DSIDefines.h50 DPP = 1 << 15, enumerator
270 DPP = 4, enumerator
798 namespace DPP {
H A DGCNHazardRecognizer.h80 int checkDPPHazards(MachineInstr *DPP);
H A DVOPInstructions.td692 // Common refers to common between DPP and DPP8
776 let DPP = 1;
791 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
795 let DecoderNamespace = "DPP";
816 let DPP = 1;
856 let DPP = 1;
866 let DecoderNamespace = "DPP";
946 let DPP = 1;
952 let AsmVariantName = AMDGPUAsmVariants.DPP;
1272 // VOP3 DPP
[all …]
H A DSIInstrFormats.td35 field bit DPP = 0;
171 let TSFlags{15} = DPP;
H A DAMDGPU.td445 "Support DPP (Data Parallel Primitives) extension"
458 "Support DPP (Data Parallel Primitives) extension"
1313 string DPP = "DPP";
1343 let Name = AMDGPUAsmVariants.DPP;
H A DSIInstrInfo.td1703 // Src2 of VOP3 DPP instructions cannot be a literal
1756 // Return type of input modifiers operand specified input operand for DPP
1762 // Return type of input modifiers operand for specified input operand for DPP
2041 // Outs for DPP
2313 0, // NumSrcArgs == 3 - No DPP for VOP3
2329 // Function that checks if instruction supports DPP and SDWA
2359 0, // 64-bit dst No DPP for 64-bit operands
2782 // Maps ordinary instructions to their DPP counterparts
2788 let ValueCols = [["DPP"]];
H A DSIInstrInfo.h627 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
631 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
H A DGCNHazardRecognizer.cpp720 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { in checkDPPHazards() argument
732 for (const MachineOperand &Use : DPP->uses()) { in checkDPPHazards()
H A DVOPCInstructions.td62 // VOPC DPP Instructions do not need an old operand
1006 // DPP Encodings
H A DVOP1Instructions.td114 // We only want to set this on the basic, non-SDWA or DPP forms.
H A DVOP3Instructions.td1082 // (they do not support SDWA or DPP).
H A DVOP2Instructions.td1046 // DPP Encodings
H A DSIInstrInfo.cpp4540 using namespace AMDGPU::DPP; in verifyInstruction()
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUInstructionSyntax.rst145 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
155 *DPP* encoding _dpp
H A DAMDGPUModifierSyntax.rst1163 DPP Modifiers
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp370 if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP) in printVOPDst()
375 } else if (Flags & SIInstrFlags::DPP) in printVOPDst()
630 return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) && in needsImpliedVcc()
647 (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) && in printOperand()
896 using namespace AMDGPU::DPP; in printDPPCtrl()
1017 using namespace llvm::AMDGPU::DPP; in printFI()
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_dpp.s108 ; DPP
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h1005 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST; in isLegal64BitDPPControl()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3230 (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) || in checkTargetMatchPredicate()
3257 AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP in getAllVariants()
3286 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP}; in getMatchedVariants()
8472 using namespace AMDGPU::DPP; in isDPPCtrl()
8671 using namespace AMDGPU::DPP; in parseDPPCtrlSel()
8719 using namespace AMDGPU::DPP; in parseDPPCtrl()
8828 using namespace llvm::AMDGPU::DPP; in cvtVOP3DPP()
8901 using namespace llvm::AMDGPU::DPP; in cvtDPP()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp415 using namespace llvm::AMDGPU::DPP; in isValidDPP8()