| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 348 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
361 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
385 (ins SReg_256:$srsrc, DMask:$dmask,
410 (ins SReg_256:$srsrc, DMask:$dmask,
516 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
555 (ins SReg_256:$srsrc, DMask:$dmask,
581 (ins SReg_256:$srsrc, DMask:$dmask,
678 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
691 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
741 (ins SReg_256:$srsrc, DMask:$dmask,
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| H A D | SILoadStoreOptimizer.cpp | 113 unsigned DMask; member
174 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
672 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
821 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
822 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1257 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1693 assert((countPopulation(CI.DMask | Paired.DMask) == Width) && in getNewOpcode()
1702 assert((CI.InstClass != MIMG || (countPopulation(CI.DMask | Paired.DMask) == in getSubRegIdxs()
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 1153 ConstantInt *DMask = cast<ConstantInt>(II.getArgOperand(DMaskIdx)); in simplifyAMDGCNMemoryIntrinsicDemanded() local
1154 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
1171 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | AMDGPULegalizerInfo.cpp | 4880 unsigned DMask = 0; in legalizeImageIntrinsic() local
4895 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
4898 } else if (DMask != 0) { in legalizeImageIntrinsic()
4899 DMaskLanes = countPopulation(DMask); in legalizeImageIntrinsic()
4922 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
4923 DMask = 0x1; in legalizeImageIntrinsic()
4925 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 1589 unsigned DMask = 0; in selectImageIntrinsic() local
1605 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
1608 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
1612 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
1613 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in selectImageIntrinsic()
1743 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
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| H A D | SIISelLowering.cpp | 989 unsigned DMask in getTgtMemIntrinsic() local
991 DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); in getTgtMemIntrinsic()
1006 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1007 unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); in getTgtMemIntrinsic()
6347 unsigned DMask; in lowerImage() local
6362 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
6365 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
6371 DMask = DMaskConst->getZExtValue(); in lowerImage()
6372 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in lowerImage()
6546 DMask = 0x1; in lowerImage()
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| H A D | SIInstrInfo.td | 1256 def DMask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
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| H A D | SIInstrInfo.cpp | 4225 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
4226 if (DMask) { in verifyInstruction()
4227 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3577 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
3578 if (DMask == 0) in validateMIMGDataSize()
3579 DMask = 1; in validateMIMGDataSize()
3583 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); in validateMIMGDataSize()
3658 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
3664 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
3676 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
3683 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 895 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
896 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); in convertMIMGInst()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 806 // Marker class for intrinsics with a DMask that determines the returned
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40457 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
40459 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
40460 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
40464 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
40479 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
40490 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
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