| /llvm-project-15.0.7/compiler-rt/lib/builtins/arm/ |
| H A D | sync-ops.h | 18 #define DMB dmb macro
20 #define DMB mcr p15, #0, r0, c7, c10, #5 macro
22 #error DMB is only supported on ARMv6+
29 DMB; \
36 DMB; \
44 DMB; \
51 DMB; \
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | invalid-barrier.s | 5 @ DMB
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| H A D | basic-arm-instructions-v8.s | 20 @ DMB (v8 barriers)
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| H A D | basic-thumb2-instructions-v8.s | 60 @ DMB (ARMv8-only barriers)
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| H A D | basic-arm-instructions.s | 817 @ DMB
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| H A D | basic-thumb2-instructions.s | 663 @ DMB
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMOptimizeBarriersPass.cpp | 67 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
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| H A D | ARM.td | 144 // True if the subtarget supports DMB / DSB data barrier instructions.
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| H A D | ARMScheduleA57.td | 118 "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
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| H A D | ARMInstrInfo.td | 5103 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
6199 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
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| H A D | ARMISelLowering.cpp | 20960 Function *DMB = Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); in makeDMB() local
20964 return Builder.CreateCall(DMB, CDomain); in makeDMB()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | atomic-ops-not-barriers.ll | 22 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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| H A D | intrinsics-memory-barrier.ll | 18 ; instructions around DMB.
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| H A D | regalloc-last-chance-recolor-with-split.mir | 282 ; CHECK-NEXT: DMB 11
511 DMB 11
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | intrinsics-memory-barrier.ll | 13 ; instructions around DMB.
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| H A D | atomic-ops-v8.ll | 1420 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrAtomics.td | 19 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
20 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
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| H A D | AArch64SchedCyclone.td | 297 // SLREX,DMB,DSB
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| H A D | AArch64SchedFalkorDetails.td | 1244 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
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| H A D | AArch64SchedKryoDetails.td | 567 (instrs DSB, DMB, CLREX)>;
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| H A D | AArch64SystemOperands.td | 77 // DMB/DSB (data barrier) instruction options.
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| H A D | AArch64InstrInfo.td | 944 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | basic-arm-instructions.txt | 515 # DMB
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| H A D | thumb2.txt | 353 # DMB
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2315 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::DMB)) in earlySelect()
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