Searched refs:DIVREM (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/ |
| H A D | scalable-divrem.ll | 44 ; CHECK-NEXT: [[DIVREM:%.*]] = udiv i64 [[ELEM]], [[V]] 45 ; CHECK-NEXT: store i64 [[DIVREM]], ptr [[ARRAYIDX]], align 8 104 ; CHECK-NEXT: [[DIVREM:%.*]] = sdiv i64 [[ELEM]], [[V]] 105 ; CHECK-NEXT: store i64 [[DIVREM]], ptr [[ARRAYIDX]], align 8 164 ; CHECK-NEXT: [[DIVREM:%.*]] = urem i64 [[ELEM]], [[V]] 224 ; CHECK-NEXT: [[DIVREM:%.*]] = srem i64 [[ELEM]], [[V]] 260 ; CHECK-NEXT: [[DIVREM:%.*]] = udiv i64 [[ELEM]], [[V]] 305 ; CHECK-NEXT: [[DIVREM:%.*]] = sdiv i64 [[ELEM]], [[V]] 378 ; CHECK-NEXT: [[DIVREM:%.*]] = udiv i64 [[ELEM]], 27 451 ; CHECK-NEXT: [[DIVREM:%.*]] = sdiv i64 [[ELEM]], 27 [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1978 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM() local 1981 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)), in LowerSDIVREM() 1982 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1)) in LowerSDIVREM()
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