| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | AlignOfTest.cpp | 164 EXPECT_EQ(alignof(D9), alignof(AlignedCharArrayUnion<D9>)); in TEST()
219 EXPECT_EQ(sizeof(D9), sizeof(AlignedCharArrayUnion<D9>)); in TEST()
220 EXPECT_EQ(sizeof(D9[1]), sizeof(AlignedCharArrayUnion<D9[1]>)); in TEST()
221 EXPECT_EQ(sizeof(D9[2]), sizeof(AlignedCharArrayUnion<D9[2]>)); in TEST()
222 EXPECT_EQ(sizeof(D9[3]), sizeof(AlignedCharArrayUnion<D9[3]>)); in TEST()
223 EXPECT_EQ(sizeof(D9[4]), sizeof(AlignedCharArrayUnion<D9[4]>)); in TEST()
224 EXPECT_EQ(sizeof(D9[5]), sizeof(AlignedCharArrayUnion<D9[5]>)); in TEST()
225 EXPECT_EQ(sizeof(D9[8]), sizeof(AlignedCharArrayUnion<D9[8]>)); in TEST()
226 EXPECT_EQ(sizeof(D9[13]), sizeof(AlignedCharArrayUnion<D9[13]>)); in TEST()
227 EXPECT_EQ(sizeof(D9[16]), sizeof(AlignedCharArrayUnion<D9[16]>)); in TEST()
[all …]
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| /llvm-project-15.0.7/llvm/test/MC/MachO/ |
| H A D | x86_64-symbols.s | 32 D9: label
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| H A D | x86_32-symbols.s | 32 D9: label
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/fuchsia/ |
| H A D | multiple-inheritance.cpp | 123 struct D9 : V15, V16 {}; struct
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-bytestring.ll | 4 …C0\C1\C2\C3\C4\C5\C6\C7\C8\C9\CA\CB\CC\CD\CE\CF\D0\D1\D2\D3\D4\D5\D6\D7\D8\D9\DA\DB\DC\DD\DE\DF\E0…
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrSVM.td | 18 // 0F 01 D9
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 106 case D11: case D10: case D9: case D8: in isARMArea3Register()
|
| H A D | ARMRegisterInfo.td | 130 def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
163 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
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| H A D | ARMCallingConv.td | 115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
|
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 55 MAP(D9, 89) \
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 94 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, in getCalleeSavedSpillSlots()
|
| H A D | HexagonRegisterInfo.td | 146 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
549 (add D11, D10, D9, D8, D3, D2, D1, D0)>;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | pal-userdata-regs.ll | 16 …0\CD\A2\CE\01\CD\A2\D5\CC\AD\CD\A2\D6\CDA\10\CD\A2\D7\04\CD\A2\D8\00\CD\A2\D9\00\CD\A2\DA\00\CD\A2…
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 139 case AArch64::D9: return AArch64::B9; in getBRegFromDReg()
179 case AArch64::B9: return AArch64::D9; in getDRegFromBReg()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.td | 364 D8, D9, D10, D11,
376 D8, D9, D10, D11,
441 D8, D9, D10, D11,
|
| H A D | AArch64PBQPRegAlloc.cpp | 67 case AArch64::D9: in isOdd()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 206 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
272 def Q4 : Rq<16, "F16", [D8, D9]>;
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 604 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
616 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 683 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
|
| H A D | AArch64MCTargetDesc.cpp | 179 {codeview::RegisterId::ARM64_D9, AArch64::D9}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 290 {codeview::RegisterId::ARM_ND9, ARM::D9}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 85 SP::D8, SP::D24, SP::D9, SP::D25,
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsCallingConv.td | 227 D7, D8, D9]>>>,
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| H A D | MipsRegisterInfo.td | 407 D8, D9,
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 685 case Hexagon::D9: in addOps()
|