| /llvm-project-15.0.7/clang/test/CXX/special/class.copy/ |
| H A D | p23-cxx11.cpp | 125 struct D8 { struct
140 template struct CopyAssign<D8>; // expected-note {{here}} argument
141 template struct MoveAssign<D8>; // expected-note {{here}}
142 template struct MoveOrCopyAssign<D8>; // expected-note {{here}}
|
| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | cond-bitlist.td | 12 def D8 : S<8>;
25 // CHECK: def D8
|
| H A D | BitsInit.td | 38 bits<2> D8 = { 0 }; // type mismatch. RHS doesn't have enough bits
77 // CHECK: bits<2> D8;
|
| H A D | if.td | 43 def D8 : S<8>;
56 // CHECK: def D8
|
| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | AlignOfTest.cpp | 59 struct D8 : S1, D4, D5 { double x[2]; }; struct
163 EXPECT_EQ(alignof(D8), alignof(AlignedCharArrayUnion<D8>)); in TEST()
218 EXPECT_EQ(sizeof(D8), sizeof(AlignedCharArrayUnion<D8>)); in TEST()
|
| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | armv8a-fpmul-error.s | 11 VFMSL.F16 Q0, D1, D8[0]
|
| /llvm-project-15.0.7/llvm/test/MC/MachO/ |
| H A D | x86_64-symbols.s | 29 D8: label
|
| H A D | x86_32-symbols.s | 29 D8: label
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 795 if (Reg == ARM::D8) in emitPrologue()
797 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
834 if (Reg == ARM::D8) in emitPrologue()
836 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
1162 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { in emitPrologue()
1519 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst()
1612 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst()
1704 unsigned DNum = I.getReg() - ARM::D8; in emitAlignedDPRCS2Spills()
1763 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills()
1875 if (I.getReg() == ARM::D8) { in emitAlignedDPRCS2Restores()
[all …]
|
| H A D | ARMBaseRegisterInfo.h | 106 case D11: case D10: case D9: case D8: in isARMArea3Register()
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/fuchsia/ |
| H A D | multiple-inheritance.cpp | 133 struct D8 : V13, V14 {}; struct
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-bytestring.ll | 4 …BF\C0\C1\C2\C3\C4\C5\C6\C7\C8\C9\CA\CB\CC\CD\CE\CF\D0\D1\D2\D3\D4\D5\D6\D7\D8\D9\DA\DB\DC\DD\DE\DF…
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | debug-info-sreg2.ll | 10 ; CHECK-NEXT: (0x{{[0-9]*[a-f]*}}, 0x{{[0-9]*[a-f]*}}): DW_OP_regx D8
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrSVM.td | 31 // 0F 01 D8
|
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 54 MAP(D8, 88) \
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 93 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | pal-userdata-regs.ll | 16 …0\CD\A2\C1\00\CD\A2\CE\01\CD\A2\D5\CC\AD\CD\A2\D6\CDA\10\CD\A2\D7\04\CD\A2\D8\00\CD\A2\D9\00\CD\A2…
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 138 case AArch64::D8: return AArch64::B8; in getBRegFromDReg()
178 case AArch64::B8: return AArch64::D8; in getDRegFromBReg()
|
| /llvm-project-15.0.7/llvm/test/DebugInfo/COFF/ |
| H A D | lines-difile.ll | 28 ; OBJ: ChecksumBytes: (8B 89 D3 B1 80 D6 A1 BC 83 E7 12 6D 5F D8 70 C3)
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.td | 364 D8, D9, D10, D11,
376 D8, D9, D10, D11,
441 D8, D9, D10, D11,
|
| H A D | AArch64PBQPRegAlloc.cpp | 116 case AArch64::D8: in isOdd()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 205 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
272 def Q4 : Rq<16, "F16", [D8, D9]>;
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 604 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
616 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 280 case D8: in getDuplexRegisterNumbering()
613 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11)); in isDblRegForSubInst()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 683 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
|