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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dd16.s7 @ D16-NEXT: vadd.f64 d1, d2, d16
8 @ D16: note: operand must be a register in range [d0, d15]
9 @ D16: note: too many operands for instruction
12 @ D16: error: operand must be a register in range [d0, d15]
13 @ D16-NEXT: vadd.f64 d1, d17, d6
16 @ D16: error: operand must be a register in range [d0, d15]
17 @ D16-NEXT: vadd.f64 d19, d7, d6
20 @ D16: error: operand must be a register in range [d0, d15]
21 @ D16-NEXT: vcvt.f64.f32 d22, s4
24 @ D16: error: operand must be a register in range [d0, d15]
[all …]
H A Dvldm-vstm-diags.s2 …e asm -o /dev/null -mattr=-d32 %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D16
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dstore-hi16.ll11 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
30 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
367 ; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
387 ; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
464 ; NO-D16-HI: v_lshrrev_b32_e32 v0, 16, v0
509 ; NO-D16-HI: v_lshrrev_b32_e32 v0, 16, v0
528 ; NO-D16-HI: v_lshrrev_b32_e32 v1, 16, v1
529 ; NO-D16-HI: ds_write_b16 v0, v1
548 ; NO-D16-HI: ds_write_b16 v0, v1
567 ; NO-D16-HI: ds_write_b16 v0, v1
[all …]
H A Dload-hi16.ll80 ; NO-D16-HI: ds_read_u16 v
95 ; NO-D16-HI: ds_read_u16 v
113 ; NO-D16-HI: ds_read_u16 v
131 ; NO-D16-HI: ds_read_u16 v
147 ; NO-D16-HI: ds_read_u16 v
165 ; NO-D16-HI: ds_read_u16 v
183 ; NO-D16-HI: ds_read_u8 v
202 ; NO-D16-HI: ds_read_i8 v
221 ; NO-D16-HI: ds_read_u8 v
242 ; NO-D16-HI: ds_read_i8 v
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dd16.txt6 # D16: warning: invalid instruction encoding
10 # D16: warning: invalid instruction encoding
14 # D16: warning: invalid instruction encoding
18 # D16: warning: invalid instruction encoding
22 # D16: warning: invalid instruction encoding
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dcond-bitlist.td13 def D16 : S<16>;
19 // CHECK: def D16
H A Dif.td44 def D16 : S<16>;
50 // CHECK: def D16
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/ARM/
H A Dlarger-subregister.mir5 # which has to be decomposed into two 64-bit register D16, D17.
11 # CHECK-NEXT: DW_OP_regx D16, DW_OP_piece 0x4, DW_OP_regx D15, DW_OP_bit_piece 0x20 0x20
H A Dsubregister-full-piece.mir31 # CHECK: DW_AT_location (DW_OP_regx D16, DW_OP_piece 0x8)
/llvm-project-15.0.7/llvm/lib/Support/
H A DARMTargetParser.cpp200 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
203 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, in getFPUFeatures()
208 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16}, in getFPUFeatures()
212 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16}, in getFPUFeatures()
216 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
506 CandidateFPU.Restriction == ARM::FPURestriction::D16) { in findDoublePrecisionFPU()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-intrinsic-vector-1op.ll27 ; CHECK-SOFTFP-BE: vmov [[D16:d[0-9]+]], r1, r0
31 ; CHECK-SOFTFP-BE: vmov r1, r0, [[D16]]
H A Dsubreg-remat.ll20 ; CHECK: vldr [[D16:d[0-9]+]],
21 ; CHECK: vstr [[D16]], [r1]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td350 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
363 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
375 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
388 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
400 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
413 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
518 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
532 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
544 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
558 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
[all …]
/llvm-project-15.0.7/llvm/test/MC/MachO/
H A Dx86_64-symbols.s53 D16: label
H A Dx86_32-symbols.s53 D16: label
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/ARM/
H A Dattribute-8.s16 @CHECK-OBJ-NEXT: Description: ARMv8-a FP-D16
H A Dattribute-6.s16 @CHECK-OBJ-NEXT: Description: VFPv4-D16
H A Dattribute-4.s16 @CHECK-OBJ-NEXT: Description: VFPv3-D16
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DARMTargetParser.def24 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None, FPURestriction::D16)
25 …-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::None, FPURestriction::D16)
29 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None, FPURestriction::D16)
31 ARM_FPU("fpv5-d16", FK_FPV5_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::D16)
34 … FK_FP_ARMV8_FULLFP16_D16, FPUVersion::VFPV5_FULLFP16, NeonSupportLevel::None, FPURestriction::D16)
H A DARMTargetParser.h150 D16, ///< Only 16 D registers enumerator
/llvm-project-15.0.7/llvm/test/DebugInfo/ARM/
H A Dpartial-subreg.ll12 ; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): DW_OP_regx D16, DW_OP_piece 0x8, DW_OP_regx D17, DW_OP_piece 0…
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h112 case D19: case D18: case D17: case D16: in isARMArea3Register()
H A DARMRegisterInfo.td140 def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
169 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
448 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on
520 // Allocate starting at non-VFP2 registers D16-D31 first.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h146 case AArch64::D16: return AArch64::B16; in getBRegFromDReg()
186 case AArch64::B16: return AArch64::D16; in getDRegFromBReg()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp92 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()

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