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/llvm-project-15.0.7/clang/test/CodeGen/
H A Dmips64-class-return.cpp7 class D0 : public B0 { class
23 extern D0 gd0;
28 D0 foo1(void) { in foo1()
43 void foo4(D0 a0) { in foo4()
H A Darm-ha-alignstack.c67 } D0; typedef
69 double g0(D0 d) { in g0()
76 D0 d = {0.0, }; in g0call()
/llvm-project-15.0.7/clang/test/OpenMP/
H A Dinterop_irbuilder.cpp10 int D0, D1; in test1() local
26 : D0, D1) nowait in test1()
29 : D0, D1) in test1()
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Denum-attr.cpp16 D0 = 1, D1 = 8 enumerator
70 case D0: break; in test()
76 case D0: break; in test()
/llvm-project-15.0.7/openmp/libomptarget/test/offloading/
H A Dinterop.c19 double D0, D2; in main() local
38 #pragma omp interop use(interop) depend(in : D0, D2) in main()
44 #pragma omp interop destroy(interop) depend(in : D0, D2) device(device_id) in main()
/llvm-project-15.0.7/clang/test/Sema/
H A Denum-attr.c16 D0 = 1, D1 = 8 enumerator
90 case D0: break; in test()
96 case D0: break; in test()
/llvm-project-15.0.7/clang/test/CXX/class/class.mem/
H A Dp13.cpp73 static int D0; member
89 struct D0 : B { using B::D0; }; // expected-error {{member 'D0' has the same name as its class}} struct
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp_convert.ll23 ; NEON: vadd.f32 [[D0:d[0-9]+]]
24 ; NEON: vcvt.s32.f32 d0, [[D0]]
35 ; NEON: vadd.f32 [[D0:d[0-9]+]]
36 ; NEON: vcvt.u32.f32 d0, [[D0]]
/llvm-project-15.0.7/mlir/test/Interfaces/InferShapedTypeOpInterface/
H A Dresolve-shaped-type-result-dims.mlir24 // CHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG_1]], %[[C0]]
26 // CHECK: return %[[D0]], %[[C5]], %[[C2]], %[[C3]], %[[D1]]
51 // CHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG_1]], %[[C0]]
53 // CHECK: return %[[D0]], %[[C5]], %[[C2]], %[[C3]], %[[D1]]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darmv8a-fpmul.s36 VFMAL.F16 D0, S1, S2
41 VFMAL.F16 D0, S1, S2[1]
H A Darmv8a-fpmul-error.s3 VFMAL.F16 D0, S1, S2[2]
9 VFMSL.F16 D0, S1, S16[0]
/llvm-project-15.0.7/llvm/test/Assembler/
H A DDIEnumeratorBig.ll7 ; CHECK: !DIEnumerator(name: "D0", value: -170141183460469231731687303715884105728)
9 !0 = !DIEnumerator(name: "D0", value: -170141183460469231731687303715884105728)
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dsize.td40 // CHECK: def D0 {
66 def D0 : D<(op)>;
70 def D4 : D<(op "string", 42, (op "sub-dag"), D0.Val)>;
H A Dself-reference.td19 // CHECK: def D0 {
20 // CHECK: D d = D0;
84 def D0 : D<"D0">;
/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-empty-virtual-base.cpp20 struct __declspec(align(16)) D0 { D0() {printf("D0 : %3d\n", ((int)(__SIZE_TYPE__)this)&0xfff);} vi… in f() function
184 struct G : virtual C0, virtual B0, virtual B1, D0, virtual C1 {
217 struct H : virtual C0, virtual B0, virtual B1, virtual D0, virtual C1 {
/llvm-project-15.0.7/llvm/test/MC/MachO/ARM/
H A Drelax-thumb2-branches.s27 @ CHECK: 00D0: 00000000 00000000 00000000 00000000 |................|
43 @ CHECK: 01D0: 00000000 00000000 00000000 00000000 |................|
/llvm-project-15.0.7/lld/test/COFF/
H A Dcombined-resources.test51 CHECK-NEXT: 00D0: 00000000 00000000 00000000 01000100 |................|
67 CHECK-NEXT: 01D0: 00000000 00000000 00000000 00000100 |................|
83 CHECK-NEXT: 02D0: C02B0000 42000000 00000000 00000000 |.+..B...........|
99 CHECK-NEXT: 03D0: 10000000 01001800 00000000 00030000 |................|
115 CHECK-NEXT: 04D0: 7DFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |}...............|
131 CHECK-NEXT: 05D0: FFFFFFFF FFFFFFFF FFFFFFFF B9B9B9F4 |................|
147 CHECK-NEXT: 06D0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
163 CHECK-NEXT: 07D0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
179 CHECK-NEXT: 08D0: FFFFFFFF 01B31800 F4BA00F4 BA00F4BA |................|
195 CHECK-NEXT: 09D0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dparallel-loops.mlir53 // CHECK-DAG: %[[D0:.*]] = memref.dim %{{.*}}, %c0
57 // CHECK: scf.parallel (%[[IV0:.*]], %[[IV1:.*]]) = (%[[C0]], %[[C0]]) to (%[[D0]], %[[D1]]) …
86 // CHECK-DAG: %[[D0:.*]] = memref.dim %{{.*}}, %c0
92 // CHECK: scf.parallel (%[[IV0:.*]], %[[IV1:.*]]) = (%[[C0]], %[[C0]]) to (%[[D0]], %[[D1]]) …
H A Ddecompose-ops.mlir36 // CHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG0]], %[[C0]]
38 // CHECK-DAG: %[[INIT1:.+]] = linalg.init_tensor [%[[D1]], %[[D0]]]
39 // CHECK-DAG: %[[INIT2:.+]] = linalg.init_tensor [%[[D0]], %[[D1]]]
82 // CANONICALIZECHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG0]], %[[C0]]
84 // CANONICALIZECHECK-DAG: %[[INIT1:.+]] = linalg.init_tensor [%[[D1]], %[[D0]]]
85 // CANONICALIZECHECK-DAG: %[[INIT2:.+]] = linalg.init_tensor [%[[D0]], %[[D1]]]
145 // CHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG0]], %[[C0]]
147 // CHECK-DAG: %[[INIT1:.+]] = linalg.init_tensor [%[[D1]], %[[D0]]]
148 // CHECK-DAG: %[[INIT2:.+]] = linalg.init_tensor [%[[D0]], %[[D1]]]
190 // CANONICALIZECHECK-DAG: %[[D0:.+]] = tensor.dim %[[ARG0]], %[[C0]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dphi-cse.ll20 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
53 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
86 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
117 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
148 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
209 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
241 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
276 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
311 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/
H A Dphi.ll17 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
50 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
83 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
114 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
145 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
206 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
238 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
273 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
308 ; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dphi-cse.ll15 ; CHECK-NEXT: store i32 [[I1]], i32* [[D0:%.*]], align 4
47 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
80 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
111 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
141 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
202 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
233 ; CHECK-NEXT: store i32 [[I1]], i32* [[D0:%.*]], align 4
267 ; CHECK-NEXT: store i32 [[I1]], i32* [[D0:%.*]], align 4
301 ; CHECK-NEXT: store i32 [[I1]], i32* [[D0:%.*]], align 4
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kCallingConv.h43 static const MCPhysReg DataRegList[] = {M68k::D0, M68k::D1, M68k::A0, in CC_M68k_Any_AssignToReg()
50 M68k::D0, in CC_M68k_Any_AssignToReg()
H A DM68kRegisterInfo.td53 defm D0 : MxDataRegister<0, "d0">;
100 // FIXME try alternative ordering like `D0, D1, A0, A1, ...`
116 def DR16_TC : MxRegClass<[i16], 16, (add D0, D1)>;
117 def DR32_TC : MxRegClass<[i32], 32, (add D0, D1)>;
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dtrivial_abi.cpp54 struct D0 : B0, B1 { struct
69 Small D0::m0() { return {}; } in m0()

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