Searched refs:Conv1 (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | deduced-return-type-cxx14.cpp | 19 struct Conv1 { struct
24 Conv1::operator auto() { return 123; } in operator auto()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9739 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in lowerToVINSERTH() local
9745 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9750 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9951 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE() local
9956 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl, in LowerVECTOR_SHUFFLE()
9960 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
9984 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE() local
9988 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
9997 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE() local
10001 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
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| /llvm-project-15.0.7/clang/lib/Sema/ |
| H A D | SemaOverload.cpp | 3689 CXXConversionDecl *Conv1 = dyn_cast_or_null<CXXConversionDecl>(Function1); in compareConversionFunctions() local
3691 if (!Conv1 || !Conv2) in compareConversionFunctions()
3694 if (!Conv1->getParent()->isLambda() || !Conv2->getParent()->isLambda()) in compareConversionFunctions()
3704 bool Block1 = Conv1->getConversionType()->isBlockPointerType(); in compareConversionFunctions()
3716 const FunctionType *Conv1FuncRet = getConversionOpReturnTyAsFunction(Conv1); in compareConversionFunctions()
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