Searched refs:CondRegs (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FlagsCopyLowering.cpp | 116 CondRegArray &CondRegs);
120 MachineOperand &FlagUse, CondRegArray &CondRegs);
124 CondRegArray &CondRegs);
644 CondRegs); in runOnMachineFunction()
735 CondRegArray CondRegs = {}; in collectCondsInRegs() local
745 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
753 return CondRegs; in collectCondsInRegs()
771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
795 CondRegArray &CondRegs) { in rewriteArithmetic() argument
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2214 SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
2215 if (CondRegs.empty()) in applyMappingImpl()
2216 CondRegs.push_back(MI.getOperand(1).getReg()); in applyMappingImpl()
2218 assert(CondRegs.size() == 1); in applyMappingImpl()
2221 const RegisterBank *CondBank = getRegBank(CondRegs[0], MRI, *TRI); in applyMappingImpl()
2229 B.buildZExt(NewCondReg, CondRegs[0]); in applyMappingImpl()
2261 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2262 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
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