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Searched refs:CondOpcode (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2103 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) { in LowerSELECT()
2115 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
2116 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
2117 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
2123 switch (CondOpcode) { in LowerSELECT()
2151 if (CondOpcode == ISD::UMULO) in LowerSELECT()
2288 if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) { in LowerBRCOND()
2311 CondOpcode = Cond.getOpcode(); in LowerBRCOND()
2312 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND()
2313 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) { in LowerBRCOND()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp3562 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); in getCondOpcode() local
3563 if (CondOpcode >= 0) // Valid Conditional opcode/instruction in getCondOpcode()
3564 return CondOpcode; in getCondOpcode()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaExpr.cpp9027 BinaryOperatorKind CondOpcode; in DiagnoseConditionalPrecedence() local
9030 if (!IsArithmeticBinaryExpr(Condition, &CondOpcode, &CondRHS)) in DiagnoseConditionalPrecedence()
9038 unsigned DiagID = BinaryOperator::isBitwiseOp(CondOpcode) in DiagnoseConditionalPrecedence()
9044 << BinaryOperator::getOpcodeStr(CondOpcode); in DiagnoseConditionalPrecedence()
9049 << BinaryOperator::getOpcodeStr(CondOpcode), in DiagnoseConditionalPrecedence()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25240 unsigned CondOpcode = Cond.getOpcode(); in LowerSELECT() local
25241 if (CondOpcode == X86ISD::SETCC || in LowerSELECT()
25242 CondOpcode == X86ISD::SETCC_CARRY) { in LowerSELECT()
25256 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || in LowerSELECT()
25257 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerSELECT()
25258 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18118 unsigned CondOpcode = SubsNode->getOpcode(); in performCONDCombine() local
18120 if (CondOpcode != AArch64ISD::SUBS) in performCONDCombine()
18179 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops); in performCONDCombine()