Searched refs:Cn (Results 1 – 15 of 15) sorted by relevance
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | strchr-2.ll | 7 @hello = constant [14 x i8] c"hello world\5Cn\00"
|
| H A D | strrchr-2.ll | 7 @hello = constant [14 x i8] c"hello world\5Cn\00"
|
| H A D | strrchr-1.ll | 7 @hello = constant [14 x i8] c"hello world\5Cn\00"
|
| H A D | memchr.ll | 7 @hello = constant [14 x i8] c"hello world\5Cn\00" 8 @hellonull = constant [14 x i8] c"hello\00world\5Cn\00"
|
| H A D | strchr-1.ll | 7 @hello = constant [14 x i8] c"hello world\5Cn\00"
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | hsa-metadata-hidden-args-v5.ll | 121 !1 = !{!"1:1:4:%d\5Cn"} 122 !2 = !{!"2:1:8:%g\5Cn"}
|
| H A D | hsa-metadata-from-llvm-ir-full-v3.ll | 1952 !100 = !{!"1:1:4:%d\5Cn"} 1953 !101 = !{!"2:1:8:%g\5Cn"}
|
| H A D | hsa-metadata-from-llvm-ir-full.ll | 1924 !100 = !{!"1:1:4:%d\5Cn"} 1925 !101 = !{!"2:1:8:%g\5Cn"}
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 614 DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N)); in visitBlock() local 615 for (auto &I : Cn) { in visitBlock() 966 DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N)); in removeBlock() local 967 for (auto &I : Cn) { in removeBlock()
|
| H A D | HexagonRegisterInfo.td | 179 // When defining more Cn registers, make sure to explicitly mark them
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/SystemZ/ |
| H A D | libcall-arg-exts.ll | 80 @hello = constant [14 x i8] c"hello world\5Cn\00"
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 779 const MCOperand &Cn = MI->getOperand(1); in printSysAlias() local 784 unsigned CnVal = Cn.getImm(); in printSysAlias()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 1676 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt), 1677 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> { 1679 bits<4> Cn; 1684 let Inst{15-12} = Cn; 1691 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2), 1692 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> { 1694 bits<4> Cn; 1699 let Inst{15-12} = Cn;
|
| H A D | AArch64InstrInfo.td | 1475 def : InstAlias<"sys $op1, $Cn, $Cm, $op2", 1476 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 3352 const uint16_t Cn = (Encoding & 0x780) >> 7; in createSysAlias() local 3360 AArch64Operand::CreateSysCR(Cn, S, getLoc(), getContext())); in createSysAlias()
|