| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4548 MVT CmpVT = N0.getSimpleValueType(); in tryVPTESTM() local 4549 MVT CmpSVT = CmpVT.getVectorElementType(); in tryVPTESTM() 4627 unsigned Scale = CmpVT.is128BitVector() ? 4 : 2; in tryVPTESTM() 4629 unsigned NumElts = CmpVT.getVectorNumElements() * Scale; in tryVPTESTM() 4630 CmpVT = MVT::getVectorVT(CmpSVT, NumElts); in tryVPTESTM() 5513 MVT CmpVT = N0.getSimpleValueType(); in Select() local 5522 switch (CmpVT.SimpleTy) { in Select() 5580 MVT CmpVT = N0.getSimpleValueType(); in Select() local 5700 (!(Mask & 0x80) || CmpVT == MVT::i8 || in Select() 5708 (!(Mask & 0x8000) || CmpVT == MVT::i16 || in Select() [all …]
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| H A D | X86FastISel.cpp | 2076 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); in X86FastEmitCMoveSelect() local 2078 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) in X86FastEmitCMoveSelect() 2311 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); in X86FastEmitPseudoSelect() local 2312 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) in X86FastEmitPseudoSelect()
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| H A D | X86ISelLowering.cpp | 23745 assert((CmpVT == MVT::i8 || CmpVT == MVT::i16 || in EmitCmp() 23746 CmpVT == MVT::i32 || CmpVT == MVT::i64) && "Unexpected VT!"); in EmitCmp() 23771 CmpVT = MVT::i32; in EmitCmp() 23783 CmpVT = MVT::i32; in EmitCmp() 42842 if (EVT(CmpVT) == VT) in combineBitcast() 51906 if (VecVT != CmpVT) in emitOrXorXorTree() 51915 if (VecVT != CmpVT) in emitOrXorXorTree() 51990 CmpVT = MVT::v64i1; in combineVectorSizedSetCCEquality() 51995 CmpVT = MVT::v16i1; in combineVectorSizedSetCCEquality() 52038 if (VecVT != CmpVT) { in combineVectorSizedSetCCEquality() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6693 EVT CmpVT; in LowerVSETCC() local 6695 CmpVT = Op0.getValueType().changeVectorElementTypeToInteger(); in LowerVSETCC() 6708 CmpVT = VT; in LowerVSETCC() 6715 unsigned CmpElements = CmpVT.getVectorNumElements() * 2; in LowerVSETCC() 6723 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged); in LowerVSETCC() 6725 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC() 6730 if (CmpVT.getVectorElementType() == MVT::i64) in LowerVSETCC() 6761 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, in LowerVSETCC() 6763 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, in LowerVSETCC() 6845 Result = DAG.getNode(ARMISD::VCMPZ, dl, CmpVT, SingleOp, in LowerVSETCC() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12119 CmpVT = MVT::v4i32; in LowerVSETCC() 12135 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG); in LowerVSETCC() 12145 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2); in LowerVSETCC() 15634 EVT CmpVT = InfoAndKind.IsAArch64 in performSetccAddFolding() local 15637 if (CmpVT != MVT::i32 && CmpVT != MVT::i64) in performSetccAddFolding() 16251 EVT CmpVT = N->getOperand(2).getValueType(); in tryConvertSVEWideCompare() local 16296 SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, DL, CmpVT, Imm); in tryConvertSVEWideCompare() 18720 EVT CmpVT = N0.getOperand(0).getValueType(); in performVSelectCombine() local 18723 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine() 21534 EVT CmpVT = Pg.getValueType(); in LowerFixedLengthVectorSetccToSVE() local [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7894 EVT CmpVT = Op.getOperand(0).getValueType(); in LowerSELECT_CC() local 7902 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC() 7904 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT), in LowerSELECT_CC() 7911 if (!CmpVT.isFloatingPoint() || !TV.getValueType().isFloatingPoint() || in LowerSELECT_CC() 7985 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC() 7995 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC() 8001 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC() 8007 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC() 8013 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4884 EVT CmpVT = LHS.getValueType(); in lowerICMPIntrinsic() local 4885 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) { in lowerICMPIntrinsic() 4915 EVT CmpVT = Src0.getValueType(); in lowerFCMPIntrinsic() local 4918 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) { in lowerFCMPIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 3702 EVT CmpVT = Tmp1.getValueType(); in ExpandNode() local 3706 EVT CCVT = getSetCCResultType(CmpVT); in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 7991 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); in visitMemCmpBCmpCall() local 7992 LoadL = DAG.getBitcast(CmpVT, LoadL); in visitMemCmpBCmpCall() 7993 LoadR = DAG.getBitcast(CmpVT, LoadR); in visitMemCmpBCmpCall()
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