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Searched refs:Chan (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td45 foreach Chan = [ "X", "Y", "Z", "W" ] in {
47 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
50 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
67 foreach Chan = [ "X", "Y", "Z", "W"] in {
69 let chan_encoding = !if(!eq(Chan, "X"), 0,
70 !if(!eq(Chan, "Y"), 1,
73 def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
79 def V01_#Chan : R600Reg_64Vertical<0, 1, Chan>;
80 def V23_#Chan : R600Reg_64Vertical<2, 3, Chan>;
89 def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>;
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H A DR600ExpandSpecialInstrs.cpp129 for (unsigned Chan = 0; Chan < 4; ++Chan) { in runOnMachineFunction() local
130 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
132 R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
134 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg); in runOnMachineFunction()
135 if (Chan > 0) { in runOnMachineFunction()
141 if (Chan != 3) in runOnMachineFunction()
195 for (unsigned Chan = 0; Chan < 4; Chan++) { in runOnMachineFunction() local
210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
230 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
236 NotLast = (Chan != 3 ); in runOnMachineFunction()
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H A DR600OptimizeVectorRegisters.cpp59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() local
61 UndefReg.push_back(Chan); in RegSeqInfo()
63 RegToChan[MO.getReg()] = Chan; in RegSeqInfo()
173 unsigned Chan) { in getReassignedChan() argument
175 if (J.first == Chan) in getReassignedChan()
196 unsigned Chan = getReassignedChan(RemapChan, Swizzle); in RebuildVector() local
202 .addImm(Chan); in RebuildVector()
203 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
204 std::vector<Register>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); in RebuildVector()
207 assert(!is_contained(UpdatedUndef, Chan) && in RebuildVector()
H A DR600MachineScheduler.cpp430 for (int Chan = 3; Chan > -1; --Chan) { in pickAlu() local
431 bool isOccupied = OccupiedSlotsMask & (1 << Chan); in pickAlu()
433 SUnit *SU = AttemptFillSlot(Chan, false); in pickAlu()
435 OccupiedSlotsMask |= (1 << Chan); in pickAlu()
H A DR600EmitClauseMarkers.cpp131 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31; in SubstituteKCacheBank() local
132 unsigned KCacheIndex = Index * 4 + Chan; in SubstituteKCacheBank()
H A DR600InstrInfo.cpp341 unsigned Chan = RI.getHWRegChan(Reg); in ExtractSrcs() local
342 Result.push_back(std::make_pair(Index, Chan)); in ExtractSrcs()
600 unsigned Chan = RI.getHWRegChan(Src.first->getReg()); in fitsConstReadLimitations() local
601 Consts.push_back((Index << 2) | Chan); in fitsConstReadLimitations()
1076 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { in reserveIndirectRegisters() local
1077 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1263 unsigned Chan = MI->getOperand(OpNum).getImm(); in printInterpAttrChan() local
1264 O << '.' << "xyzw"[Chan & 0x3]; in printInterpAttrChan()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp6926 StringRef Chan = Str.take_back(2); in parseInterpAttr() local
6927 int AttrChan = StringSwitch<int>(Chan) in parseInterpAttr()
6951 SMLoc SChan = SMLoc::getFromPointer(Chan.data()); in parseInterpAttr()