Searched refs:CastVT (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 2564 EVT CastVT = CastVal.getValueType(); in BitcastToInt_ATOMIC_SWAP() local
2567 = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT, in BitcastToInt_ATOMIC_SWAP()
2568 DAG.getVTList(CastVT, MVT::Other), in BitcastToInt_ATOMIC_SWAP()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3981 EVT CastVT = getPromotedVTForPredicate(InVT); in LowerVectorINT_TO_FP() local
3982 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
3997 MVT CastVT = in LowerVectorINT_TO_FP() local
4001 In = DAG.getNode(Opc, dl, {CastVT, MVT::Other}, in LowerVectorINT_TO_FP()
4007 In = DAG.getNode(Opc, dl, CastVT, In); in LowerVectorINT_TO_FP()
4013 EVT CastVT = VT.changeVectorElementTypeToInteger(); in LowerVectorINT_TO_FP() local
4014 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
10040 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
10044 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
10348 MVT CastVT; in constructDup() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 19613 Cond = DAG.getBitcast(CastVT, Cond); in LowerVSELECT()
19614 LHS = DAG.getBitcast(CastVT, LHS); in LowerVSELECT()
19615 RHS = DAG.getBitcast(CastVT, RHS); in LowerVSELECT()
24403 Cmp = DAG.getBitcast(CastVT, Cmp); in LowerVSETCC()
25717 MVT CastVT = MVT::getVectorVT(StVT, 2); in LowerStore() local
49150 EVT CastVT = VT; in reduceMaskedLoadToScalarLoad() local
49287 Value = DAG.getBitcast(CastVT, Value); in reduceMaskedStoreToScalarStore()
51985 EVT CastVT = VecVT; in combineVectorSizedSetCCEquality() local
51992 CastVT = VecVT; in combineVectorSizedSetCCEquality()
51996 CastVT = OpSize == 512 ? VecVT : in combineVectorSizedSetCCEquality()
[all …]
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| H A D | X86InstrAVX512.td | 1856 X86VectorVTInfo CastVT> {
1860 (CastVT.VT _.RC:$src1))),
1862 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1868 (CastVT.VT _.RC:$src1))),
1870 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1875 (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))),
1877 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4860 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT); in lowerIntrinsicLoad() local
4861 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad()
4862 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT, in lowerIntrinsicLoad()
6181 static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, in padEltsToUndef() argument
6196 return DAG.getBuildVector(CastVT, DL, Elts); in padEltsToUndef()
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