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Searched refs:CarryRC (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1844 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in computeBase() local
1845 Register CarryReg = MRI->createVirtualRegister(CarryRC); in computeBase()
1846 Register DeadCarryReg = MRI->createVirtualRegister(CarryRC); in computeBase()
H A DSIInstrInfo.cpp6241 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in moveToVALU() local
6244 if (!MRI.constrainRegClass(CarryInReg, CarryRC)) { in moveToVALU()
6245 Register NewCarryReg = MRI.createVirtualRegister(CarryRC); in moveToVALU()
6770 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in splitScalar64BitAddSub() local
6776 Register CarryReg = MRI.createVirtualRegister(CarryRC); in splitScalar64BitAddSub()
6777 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC); in splitScalar64BitAddSub()
H A DAMDGPUInstructionSelector.cpp373 const TargetRegisterClass *CarryRC = TRI.getWaveMaskRegClass(); in selectG_ADD_SUB() local
374 Register CarryReg = MRI->createVirtualRegister(CarryRC); in selectG_ADD_SUB()
381 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead) in selectG_ADD_SUB()
H A DSIISelLowering.cpp4060 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in EmitInstrWithCustomInserter() local
4065 Register CarryReg = MRI.createVirtualRegister(CarryRC); in EmitInstrWithCustomInserter()
4066 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC); in EmitInstrWithCustomInserter()