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Searched refs:CSRs (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvaargs-prolog-insert.ll4 ; Check the prolog won't be sunk across the save of CSRs.
H A Dseh-catch-all-win32.ll55 ; Ensure that we push *all* the CSRs, since they are clobbered by the
H A Dshrink-wrapping-vla.ll76 ; Check that llvm.stackrestore() happens before CSRs are popped off the stack
H A Dcxx_tlscc64.ll118 ; Make sure at O0, we don't generate spilling/reloading of the CSRs.
H A Dx86-no_callee_saved_registers.ll21 ; Calling a routine with no CSRs means the caller has to spill a bunch
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dlivephysregs.mir4 # recalculated list if okay and contains all the non-saved and saved CSRs.
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-custom-call-saved-reg.ll60 ; Check that callee preserves additional CSRs.
103 ; Check that caller doesn't shy away from allocating additional CSRs.
H A Dshrink-wrapping-vla.ll76 ; Check that llvm.stackrestore() happens before CSRs are popped off the stack
H A Dcxx-tlscc.ll159 ; Make sure at O0, we don't generate spilling/reloading of the CSRs.
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drvf-user-csr-names.s20 # User Floating Pont CSRs
H A Drvv-user-csr-names.s14 # User Vector CSRs
H A Duser-csr-names.s133 # User Floating Pont CSRs
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td339 // the order of CSRs in CSR_iOS.
343 // CSRs that are handled by prologue, epilogue.
346 // CSRs that are handled explicitly via copies.
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp624 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { in setCalleeSavedRegs() argument
628 append_range(UpdatedCSRs, CSRs); in setCalleeSavedRegs()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td91 // User Floating-Point CSRs
349 // User Vector CSRs
/llvm-project-15.0.7/llvm/test/MC/COFF/
H A Dcv-fpo-realign.s3 # Test for .cv_fpo_stackalign. We should generate FPO data that restores CSRs
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp152 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF); in UpdateCustomCalleeSavedRegs() local
154 for (const MCPhysReg *I = CSRs; *I; ++I) in UpdateCustomCalleeSavedRegs()
H A DAArch64CallingConvention.td474 // CSRs that are handled by prologue, epilogue.
478 // CSRs that are handled explicitly via copies.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Darm-shrink-wrapping-linux.ll11 ; Check that we do not restore the before having used the saved CSRs.
13 ; The exit block of the loop happens to also lead to defs/uses of CSRs.
H A Dcxx-tlscc.ll102 ; Make sure at O0, we don't generate spilling/reloading of the CSRs.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dstack-realign.ll270 call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
311 call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
H A Dcallee-frame-setup.ll596 call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
631 call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
668 call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td134 // The CSRs & scratch-registers are interleaved at a split boundary of 8.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h252 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dzos-prologue-epilog.ll22 ; Spill all GPR CSRs

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