| /llvm-project-15.0.7/compiler-rt/lib/scudo/standalone/ |
| H A D | linux.cpp | 138 cpu_set_t CPUs; in getNumberOfCPUs() local
141 if (sched_getaffinity(0, sizeof(cpu_set_t), &CPUs) != 0) in getNumberOfCPUs()
143 return static_cast<u32>(CPU_COUNT(&CPUs)); in getNumberOfCPUs()
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| /llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/ |
| H A D | cpu.ll | 3 ; CHECK: Available CPUs for this target:
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | mftb.ll | 2 ; For CPUs 601 and pwr3, the mftb instruction should be emitted.
3 ; On all other CPUs (including generic, ppc, ppc64), the mfspr instruction
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| /llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ |
| H A D | mattr-mcpu-help.test | 6 # CHECK: Available CPUs for this target:
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SchedPredicates.td | 65 // on recent Intel CPUs.
77 // on recent Intel CPUs.
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| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/ |
| H A D | cpus-no-mips64.ll | 1 ; Check that we reject 64-bit mode on 32-bit only CPUs.
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| H A D | cpus.ll | 61 ; Check that we reject CPUs that are not implemented.
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | cpus-no-x86_64.ll | 1 ; Check that we reject 64-bit mode on 32-bit only CPUs.
|
| H A D | v4i32load-crash.ll | 6 ;This instruction is not legal for X86 CPUs with sse < 'sse4.1'.
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| H A D | sbb-zero-idiom.ll | 8 ; And check that CPUs have included the attribute as expected.
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| H A D | fold-vex.ll | 15 ; unless specially configured on some CPUs such as AMD Family 10H.
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| H A D | cpus-other.ll | 8 ; Now ensure the error message doesn't occur for valid CPUs.
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| H A D | cpus-amd-no-x86_64.ll | 1 ; Check that we reject 64-bit mode on 32-bit only CPUs.
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| H A D | cpus-intel-no-x86_64.ll | 1 ; Check that we reject 64-bit mode on 32-bit only CPUs.
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| /llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/ |
| H A D | cpus.ll | 1 ; This tests that llc accepts all valid WebAssembly CPUs.
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | arm-thumb-cpus.s | 25 @ Make sure correct diagnostics are given for CPUs without support for
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetPfmCounters.td | 49 // Declares the default binding for unbound CPUs for the target.
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| /llvm-project-15.0.7/llvm/docs/tutorial/MyFirstLanguageFrontend/ |
| H A D | LangImpl08.rst | 87 To see which features and CPUs that LLVM knows about, we can use
93 Available CPUs for this target:
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| /llvm-project-15.0.7/lldb/test/Shell/Register/ |
| H A D | x86-fp-write.test | 16 # note: segment registers are not supported on all CPUs
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| /llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/ |
| H A D | sanitizer_linux_libcdep.cpp | 825 cpu_set_t CPUs; in GetNumberOfCPUs()
826 CHECK_EQ(sched_getaffinity(0, sizeof(cpu_set_t), &CPUs), 0); in GetNumberOfCPUs()
827 return CPU_COUNT(&CPUs); in GetNumberOfCPUs()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | cpus.ll | 1 ; This tests that llc accepts all valid AArch64 CPUs
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | YamlIO.rst | 292 For instance, suppose you had an enumeration of CPUs and a struct with it as
297 enum CPUs {
304 CPUs cpu;
309 ScalarEnumerationTraits specialization on CPUs, which can then be used
319 struct ScalarEnumerationTraits<CPUs> {
320 static void enumeration(IO &io, CPUs &value) {
737 CPUs cpu;
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| H A D | HowToBuildOnARM.rst | 18 ARM encompasses a wide variety of CPUs; this advice is primarily based
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| /llvm-project-15.0.7/libc/benchmarks/ |
| H A D | RATIONALE.md | 59 Modern CPUs are [out of
103 inconsistent across micro-architectures and imprecise on modern CPUs for small
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| /llvm-project-15.0.7/llvm/docs/CommandGuide/ |
| H A D | lli.rst | 85 the current architecture. For a list of available CPUs, use:
|