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Searched refs:CONST32 (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dsplit-const32-const64.ll3 ; Check that CONST32/CONST64 instructions are 'not' generated when the
12 ; CHECK-NOT: CONST32
H A Dstruct_args_large.ll3 ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp76 if (Opc == Hexagon::CONST32) { in runOnMachineFunction()
H A DHexagonPseudo.td65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
66 "$Rd = CONST32(#$v)", []>;
H A DHexagonBitTracker.cpp209 case CONST32: in evaluate()
321 case CONST32: in evaluate()
H A DHexagonISelLowering.h37 CONST32 = OP_BEGIN, enumerator
H A DHexagonISelDAGToDAG.cpp1403 if (!UseGP && GAOpc != HexagonISD::CONST32) in SelectGlobalAddress()
1422 case HexagonISD::CONST32: in SelectGlobalAddress()
1872 return V.getOpcode() == HexagonISD::CONST32 || in isTargetConstant()
H A DHexagonISelLowering.cpp1232 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA); in LowerGLOBALADDRESS()
1330 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA); in LowerToTLSInitialExecModel()
1366 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA); in LowerToTLSLocalExecModel()
1391 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA); in LowerToTLSGeneralDynamicModel()
1890 case HexagonISD::CONST32: return "HexagonISD::CONST32"; in getTargetNodeName()
H A DHexagonAsmPrinter.cpp345 case Hexagon::CONST32: in HexagonProcessInstruction()
H A DHexagonConstPropagation.cpp1982 case Hexagon::CONST32: in evaluate()
2338 case Hexagon::CONST32: in rewrite()
H A DHexagonHardwareLoops.cpp1514 case Hexagon::CONST32: in checkForImmediate()
H A DHexagonBitSimplify.cpp1431 case Hexagon::CONST32: in isTfrConst()
H A DHexagonPatterns.td396 def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1441 case Hexagon::CONST32: in processInstruction()