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Searched refs:COND1 (Results 1 – 25 of 43) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/Util/
H A Dlibcalls-shrinkwrap-double.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
72 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
82 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
92 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
102 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
128 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
204 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
H A Dlibcalls-shrinkwrap-float.ll11 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -8.900000e+01
13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
21 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -1.030000e+02
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
83 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
93 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
103 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
H A Dlibcalls-shrinkwrap-long-double.ll11 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB174000000000000
13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
21 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB21C000000000000
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
83 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
93 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
103 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
/llvm-project-15.0.7/clang/test/CoverageMapping/
H A Dbranch-macros.cpp6 #define COND1 (a == b) macro
8 #define COND3 (COND1 && COND2)
9 #define COND4 (COND3 ? COND2 : COND1)
22 …bool c = COND1 && COND2; // CHECK: Branch,File 1, [[@LINE-16]]:15 -> [[@LINE-16]]:23 = #1, (#0 - #… in func()
/llvm-project-15.0.7/llvm/test/tools/llvm-cov/
H A Dbranch-macros.cpp5 #define COND1 (a == b) macro
7 #define COND3 (COND1 && COND2)
8 #define COND4 (COND3 ? COND2 : COND1)
17 bool c = COND1 && COND2; // CHECK: | | | Branch ([[@LINE-12]]:15): [True: 1, False: 2] in func()
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dpr49495.ll7 ; CHECK-NEXT: [[COND1:%.*]] = icmp ne ptr [[A:%.*]], [[B:%.*]]
10 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND1]], i1 [[COND2]], i1 false
23 ; CHECK-NEXT: [[COND1:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
26 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND1]], i1 [[COND2]], i1 false
/llvm-project-15.0.7/llvm/test/Transforms/JumpThreading/
H A Dfreeze-impliescond.ll86 ; CHECK-NEXT: [[COND1:%.*]] = icmp slt i32 0, [[X:%.*]]
87 ; CHECK-NEXT: [[COND:%.*]] = and i1 [[COND1]], [[COND2:%.*]]
93 ; CHECK-NEXT: [[COND_FR:%.*]] = freeze i1 [[COND1]]
98 ; CHECK-NEXT: [[COND_FR2:%.*]] = freeze i1 [[COND1]]
134 ; CHECK-NEXT: [[COND1:%.*]] = icmp slt i32 0, [[X:%.*]]
135 ; CHECK-NEXT: [[COND:%.*]] = and i1 [[COND1]], [[COND2:%.*]]
142 ; CHECK-NEXT: [[COND_FR2:%.*]] = freeze i1 [[COND1]]
H A Dthread-two-bbs-threshold.ll13 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[COND1:%.*]], 0
/llvm-project-15.0.7/llvm/test/Transforms/SimpleLoopUnswitch/
H A Dtrivial-unswitch-freeze-individual-conditions.ll10 ; CHECK-NEXT: [[COND1_FR:%.*]] = freeze i1 [[COND1:%.*]]
49 ; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[COND4_FR]], [[COND1:%.*]]
86 ; CHECK-NEXT: [[COND1_FR:%.*]] = freeze i1 [[COND1:%.*]]
125 ; CHECK-NEXT: [[COND1_FR:%.*]] = freeze i1 [[COND1:%.*]]
160 ; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[COND4_FR]], [[COND1:%.*]]
193 ; CHECK-NEXT: [[COND1_FR:%.*]] = freeze i1 [[COND1:%.*]]
227 ; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[COND4:%.*]], [[COND1:%.*]]
H A Dtrivial-unswitch-logical-and-or.ll13 ; CHECK-NEXT: [[COND_AND1:%.*]] = and i1 [[COND2:%.*]], [[COND1:%.*]]
41 ; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[COND2:%.*]], [[COND1:%.*]]
76 ; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[COND2:%.*]], [[COND1:%.*]]
114 ; CHECK-NEXT: [[COND_AND1:%.*]] = or i1 [[COND2:%.*]], [[COND1:%.*]]
146 ; CHECK-NEXT: [[COND1_FR:%.*]] = freeze i1 [[COND1:%.*]]
204 ; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP1]], [[COND1:%.*]]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Darc-loadweakretained-release.m53 // CHECK: [[COND1:%.*]] = phi i8**
54 // CHECK-NEXT: [[ICRISNULL:%.*]] = icmp eq i8** [[COND1]], null
65 // CHECK-NEXT: [[ICRISNULL1:%.*]] = icmp eq i8** [[COND1]], null
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Drewrite-loop-exit-value.ll66 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32* [[VAR:%.*]], null
76 ; CHECK-NEXT: br i1 [[COND1]], label [[HEADER_BACKEDGE]], label [[EXIT:%.*]]
104 ; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LOOP:%.*]], label [[EXIT:%.*]]
132 ; CHECK-NEXT: [[COND1:%.*]] = load volatile i1, i1* [[ADDR:%.*]], align 1
133 ; CHECK-NEXT: br i1 [[COND1]], label [[LOOP]], label [[MAYBE:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcall_nonnull_arg.ll10 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32* [[A:%.*]], null
11 ; CHECK-NEXT: br i1 [[COND1]], label [[DEAD:%.*]], label [[NOT_NULL:%.*]]
H A Dxor-of-icmps-with-extra-uses.ll132 ; CHECK-NEXT: [[COND1:%.*]] = icmp sgt i32 [[X]], -32768
136 ; CHECK-NEXT: [[RES:%.*]] = xor i1 [[COND0]], [[COND1]]
153 ; CHECK-NEXT: [[COND1:%.*]] = icmp sgt i32 [[X]], -32768
154 ; CHECK-NEXT: [[RES:%.*]] = xor i1 [[COND0]], [[COND1]]
/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Dstride_more_than_1.ll19 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
20 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
84 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
85 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
150 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
151 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
258 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp sgt i32 100, %exit.preloop.at
259 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit
324 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 2147483640, %exit.preloop.at
325 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit
[all …]
H A Dempty_ranges.ll31 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ult i32 %idx.next, 10
32 ; CHECK-NEXT: br i1 [[COND1]], label %loop, label %main.exit.selector
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dpr42422-phi-of-ops.ll50 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32 [[CLEANUP_DEST15]], 0
51 ; CHECK-NEXT: br i1 [[COND1]], label [[FOR_INC17]], label [[CLEANUP20:%.*]]
58 ; CHECK-NEXT: [[PHIOFOPS:%.*]] = phi i1 [ true, [[FOR_END19]] ], [ [[COND1]], [[CLEANUP14]] ]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-icmp.mir23 # GCN-NEXT: [[COND1:%[0-9]+]]:sreg_32 = COPY $scc
26 # GCN: $scc = COPY [[COND1]]
135 # GCN: [[COND1:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]]
137 # GCN: V_CNDMASK_B32_e64 0, [[VGPR5]], 0, [[VGPR4]], [[COND1]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dunroll-loop-invalidation.ll56 ; CHECK: %[[COND1:.*]] = icmp eq i32 %{{.*}}, %inner1.count
57 ; CHECK: br i1 %[[COND1]],
H A D2011-08-08-PhiUpdate.ll11 ; CHECK-NEXT: [[COND1:%.*]] = call zeroext i1 @check()
12 ; CHECK-NEXT: br i1 [[COND1]], label [[IF_THEN:%.*]], label [[IF_ELSE_LR_PH:%.*]]
150 ; CHECK-NEXT: [[COND1:%.*]] = call zeroext i1 @check()
151 ; CHECK-NEXT: br i1 [[COND1]], label [[RETURN:%.*]], label [[IF_END:%.*]]
H A Druntime-loop-branchweight.ll7 ; CHECK: br i1 [[COND1:%.*]], label %for.end.loopexit.unr-lcssa.loopexit, label %for.body, !prof ![…
/llvm-project-15.0.7/llvm/test/Transforms/MergeICmps/X86/
H A Daddressspaces.ll66 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[A1]], [[B1]]
69 ; CHECK-NEXT: [[NECESSARY:%.*]] = phi i1 [ [[COND1]], [[BB2]] ], [ false, [[BB1]] ]
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dcontrol-flow-ops-to-llvm.mlir48 // CHECK: %[[COND1:.*]] = llvm.mlir.constant(true) : i1
53 // CHECK: llvm.cond_br %[[COND1]], ^bb1(%{{.*}}, %[[COND2]] : i32, i1), ^bb2
/llvm-project-15.0.7/llvm/test/Transforms/MakeGuardsExplicit/
H A Dbasic.ll30 ; CHECK-NEXT: [[EXIPLICIT_GUARD_COND:%.*]] = and i1 [[COND1:%.*]], [[WIDENABLE_COND]]
65 ; CHECK-NEXT: [[EXIPLICIT_GUARD_COND:%.*]] = and i1 [[COND1:%.*]], [[WIDENABLE_COND]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopInterchange/
H A Dupdate-condbranch-duplicate-successors.ll30 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 1000
100 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 1000

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