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/llvm-project-15.0.7/llvm/test/Transforms/Util/
H A Dlibcalls-shrinkwrap-double.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
72 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
82 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
92 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
102 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
128 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
204 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
H A Dlibcalls-shrinkwrap-float.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
51 ; CHECK: [[COND:%[0-9]+]] = fcmp ogt float %value, 8.800000e+01
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
83 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
93 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
103 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
111 ; CHECK: [[COND:%[0-9]+]] = fcmp olt float %value, 1.000000e+00
[all …]
H A Dlibcalls-shrinkwrap-long-double.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
51 ; CHECK: [[COND:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB170000000000000
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
83 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
93 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
103 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
111 ; CHECK: [[COND:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xK3FFF8000000000000000
[all …]
H A Dflattencfg.ll33 ; CHECK-NEXT: [[COND:%[a-z0-9]+]] = and i1 %0, %1
34 ; CHECK-NEXT: br i1 [[COND]], label %bb4, label %bb3
62 ; CHECK-NEXT: [[COND:%[a-z0-9]+]] = or i1 %a_eq_0, %a_eq_1
63 ; CHECK-NEXT: br i1 [[COND]], label %bb2, label %bb3
96 ; CHECK-NEXT: [[COND:%[a-z0-9]+]] = or i1 %cmp.x, %cmp.y
97 ; CHECK-NEXT: br i1 [[COND]], label %if.then.y, label %exit
128 ; CHECK-NEXT: [[COND:%[a-z0-9]+]] = and i1 %cmp.x, %cmp.y
129 ; CHECK-NEXT: br i1 [[COND]], label %exit, label %if.else.y
160 ; CHECK-NEXT: [[COND:%[a-z0-9]+]] = and i1 %cmp.x, %cmp.y
161 ; CHECK-NEXT: br i1 [[COND]], label %exit, label %if.then.y
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbinop-select.ll11 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
26 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
41 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]
56 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]
70 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]
112 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 42, [[COND]]
138 ; CHECK-NEXT: [[DIV:%.*]] = udiv i32 42, [[COND]]
151 ; CHECK-NEXT: [[DIV:%.*]] = srem i32 42, [[COND]]
164 ; CHECK-NEXT: [[DIV:%.*]] = urem i32 42, [[COND]]
177 ; CHECK-NEXT: tail call void @use(i32 [[COND]])
[all …]
H A Dpull-conditional-binop-through-shift.ll10 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
22 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
35 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
47 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
60 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
72 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
85 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
186 ; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
198 ; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
288 ; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
[all …]
H A Dicmp-bc-vec.ll17 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
18 ; CHECK-NEXT: ret i1 [[COND]]
29 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
30 ; CHECK-NEXT: ret i1 [[COND]]
52 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
53 ; CHECK-NEXT: ret i1 [[COND]]
64 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
65 ; CHECK-NEXT: ret i1 [[COND]]
80 ; CHECK-NEXT: ret i1 [[COND]]
95 ; CHECK-NEXT: ret i1 [[COND]]
[all …]
H A Dicmp-bc-vec-inseltpoison.ll17 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
18 ; CHECK-NEXT: ret i1 [[COND]]
29 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
30 ; CHECK-NEXT: ret i1 [[COND]]
52 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
53 ; CHECK-NEXT: ret i1 [[COND]]
64 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
65 ; CHECK-NEXT: ret i1 [[COND]]
80 ; CHECK-NEXT: ret i1 [[COND]]
95 ; CHECK-NEXT: ret i1 [[COND]]
[all …]
H A Dselect-binop-foldable-floating-point.ll6 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float [[B:%.*]], float -0.000000e+00
17 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float -0.000000e+00, float [[B:%.*]]
28 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float [[B:%.*]], float -0.000000e+00
39 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float -0.000000e+00, float [[B:%.*]]
83 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float [[B:%.*]], float 1.000000e+00
94 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float 1.000000e+00, float [[B:%.*]]
105 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float [[B:%.*]], float 1.000000e+00
116 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float 1.000000e+00, float [[B:%.*]]
127 ; CHECK-NEXT: [[C:%.*]] = select i1 [[COND:%.*]], float [[B:%.*]], float 0.000000e+00
195 ; CHECK-NEXT: [[D:%.*]] = select i1 [[COND:%.*]], float [[C]], float [[A]]
[all …]
H A Dselect-ctlz-to-cttz.ll20 ; CHECK-NEXT: ret i32 [[COND]]
34 ; CHECK-NEXT: ret i32 [[COND]]
48 ; CHECK-NEXT: ret <2 x i32> [[COND]]
67 ; CHECK-NEXT: ret i32 [[COND]]
82 ; CHECK-NEXT: ret i32 [[COND]]
98 ; CHECK-NEXT: ret i32 [[COND]]
113 ; CHECK-NEXT: ret i64 [[COND]]
134 ; CHECK-NEXT: ret i32 [[COND]]
153 ; CHECK-NEXT: ret i64 [[COND]]
172 ; CHECK-NEXT: ret i64 [[COND]]
[all …]
H A Dsimple_phi_condition.ll13 ; CHECK-NEXT: ret i1 [[COND]]
38 ; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true
91 ; CHECK-NEXT: ret i1 [[COND]]
132 ; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true
171 ; CHECK-NEXT: ret i1 [[COND]]
282 ; CHECK-NEXT: ret i8 [[COND]]
323 ; CHECK-NEXT: ret i8 [[COND]]
397 ; CHECK-NEXT: ret i8 [[COND]]
484 ; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[COND]], -1
553 ; CHECK-NEXT: switch i8 [[COND:%.*]], label [[MERGE:%.*]] [
[all …]
H A Dusub-overflow-known-by-implied-cond.ll65 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
92 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
121 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
149 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
176 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
236 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
237 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]]
266 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
297 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]]
361 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[COND]], [[COND2:%.*]]
[all …]
H A Dnonnull-select.ll23 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
32 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* null, i32* [[P:%.*]]
41 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
50 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* null, i32* [[P:%.*]]
60 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
71 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* null, i32* [[P:%.*]]
82 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
93 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* null, i32* [[P:%.*]]
H A Dfcmp-select.ll69 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[X]], double [[Y]]
70 ; CHECK-NEXT: ret double [[COND]]
82 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[Y]], double [[X]]
83 ; CHECK-NEXT: ret double [[COND]]
95 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[X]], double -1.000000e+00
96 ; CHECK-NEXT: ret double [[COND]]
108 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double -1.000000e+00, double [[X]]
109 ; CHECK-NEXT: ret double [[COND]]
H A Dicmp-constant-phi.ll7 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
15 ; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[COND]], true
39 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
47 ; CHECK-NEXT: ret i1 [[COND]]
70 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
101 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
109 ; CHECK-NEXT: ret i1 [[COND]]
132 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
163 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
196 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dnumsignbits-from-assume.ll7 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
8 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
22 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
23 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
37 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
38 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
52 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
53 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
68 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
83 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/
H A Dand_or.ll8 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
33 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
34 ; CHECK-NEXT: [[AND_COND:%.*]] = and i1 [[COND]], [[C:%.*]]
61 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
89 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
90 ; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[COND]], [[C:%.*]]
117 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
145 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
146 ; CHECK-NEXT: [[AND_COND1:%.*]] = and i1 [[COND]], [[C1:%.*]]
175 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dspeculate-cttz-ctlz.ll13 ; BMI-NEXT: ret i64 [[COND]]
27 ; GENERIC-NEXT: ret i64 [[COND]]
48 ; BMI-NEXT: ret i32 [[COND]]
84 ; BMI-NEXT: ret i16 [[COND]]
232 ; ALL-NEXT: ret i64 [[COND]]
255 ; ALL-NEXT: ret i32 [[COND]]
278 ; ALL-NEXT: ret i64 [[COND]]
301 ; ALL-NEXT: ret i32 [[COND]]
324 ; ALL-NEXT: ret i16 [[COND]]
347 ; ALL-NEXT: ret i16 [[COND]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_select_cmp.ll9 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 109, i32 [[CONV]]
10 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
28 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
47 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
66 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
85 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
104 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
123 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
172 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
187 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
[all …]
H A Dtrunc_select.ll9 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[A:%.*]], i16 [[B:%.*]]
23 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i8 [[A:%.*]], i8 [[B:%.*]]
39 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[CONV0]], i16 [[CONV1]]
54 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 109, i16 [[A:%.*]]
68 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 4, i16 [[A:%.*]]
81 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i8 109, i8 [[A:%.*]]
95 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i8 4, i8 [[A:%.*]]
110 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]
126 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i16 [[SUB]], i16 [[CONV]]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dfcmp-select.ll57 ; CHECK-NEXT: ret double [[COND]]
70 ; CHECK-NEXT: ret float [[COND]]
83 ; CHECK-NEXT: ret double [[COND]]
96 ; CHECK-NEXT: ret double [[COND]]
198 ; CHECK-NEXT: ret double [[COND]]
212 ; CHECK-NEXT: ret <2 x double> [[COND]]
222 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[X]], double [[Y]]
223 ; CHECK-NEXT: ret double [[COND]]
234 ; CHECK-NEXT: ret double [[COND]]
245 ; CHECK-NEXT: ret double [[COND]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CanonicalizeFreezeInLoops/
H A Donephi.ll15 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
16 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
42 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
43 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
70 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
71 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
100 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
101 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
131 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
221 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/ARM/
H A Dbranch-fold-threshold.ll19 ; CHECK-NEXT: ret i32 [[COND]]
52 ; CHECK-NEXT: ret i32 [[COND]]
85 ; CHECK-NEXT: ret i32 [[COND]]
118 ; CHECK-NEXT: ret i32 [[COND]]
151 ; CHECK-NEXT: ret i32 [[COND]]
185 ; THUMB-NEXT: ret i32 [[COND]]
199 ; ARM-NEXT: ret i32 [[COND]]
233 ; THUMB-NEXT: ret i32 [[COND]]
247 ; ARM-NEXT: ret i32 [[COND]]
326 ; ARM-NEXT: ret i32 [[COND]]
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dcontrol-flow-ops-to-llvm.mlir35 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : i1
37 // CHECK: lvm.cond_br %[[COND]], ^bb1, ^bb2
55 // CHECK: ^bb1(%{{.*}}: i32, %[[COND:.*]]: i1):
57 // CHECK: llvm.cond_br %[[COND]], ^bb3, ^bb4(%{{.*}}, %{{.*}} : i32, i32)
93 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : i1
94 // CHECK: llvm.cond_br %[[COND]], ^[[BB2:.*]], ^[[BB4:.*]]
147 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : i1
149 // CHECK: llvm.cond_br %[[COND]], ^bb1, ^bb2
167 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : i1
169 // CHECK: llvm.cond_br %[[COND]], ^bb1, ^bb2
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dassumes_info.ll9 ; CHECK-SAME: (i1 [[COND:%.*]]) #[[ATTR0:[0-9]+]] {
11 ; CHECK-NEXT: call void @foo(i1 [[COND]])
25 ; IS__TUNIT____-SAME: (i1 [[COND:%.*]]) #[[ATTR1]] {
27 ; IS__TUNIT____-NEXT: call void @baz(i1 [[COND]])
31 ; IS__CGSCC____-SAME: (i1 [[COND:%.*]]) #[[ATTR1]] {
33 ; IS__CGSCC____-NEXT: call void @baz(i1 [[COND]]) #[[ATTR1]]
55 ; IS__TUNIT____-SAME: (i1 [[COND:%.*]]) #[[ATTR1]] {
57 ; IS__TUNIT____-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[COND]], false
67 ; IS__CGSCC____-SAME: (i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] {
69 ; IS__CGSCC____-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[COND]], false

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