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Searched refs:COMBINE (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dmicrosoft-ext.c30 #define COMBINE(...) __VA_ARGS__ macro
31 #define WRAPPED_TEST(...) COMBINE(THIRD_ARGUMENT(__VA_ARGS__, 1, 2))
/llvm-project-15.0.7/llvm/test/Transforms/AddDiscriminators/
H A Doneline.ll41 ; CHECK: store i32 99, ptr %1, align 4, !dbg ![[COMBINE:[0-9]+]]
44 ; CHECK: br label %10, !dbg ![[COMBINE]]
99 ; CHECK: ![[COMBINE]] = !DILocation(line: 2, column: 42, scope: ![[COMBINEBLOCK:[0-9]+]])
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1888 case HexagonISD::COMBINE: return "HexagonISD::COMBINE"; in getTargetNodeName()
2262 SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2269 SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2558 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L}); in buildVector64()
2676 ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in insertVector()
2845 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1), in LowerCONCAT_VECTORS()
2869 W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
2894 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
H A DHexagonISelLowering.h55 COMBINE, enumerator
H A DHexagonISelLoweringHVX.cpp1130 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg()
1193 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
1852 HexagonISD::COMBINE, dl, MVT::i64, {Words[i+1], Words[i]}); in LowerHvxBitcast()
H A DHexagonPatterns.td1043 def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon.td993 def COMBINE : NoTestOpInst<"vcombine", "Q..", "dPl", OP_CONC>;