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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsic-opts-counting-elems.ll101 ; CHECK-NEXT: [[CNT:%.*]] = call i64 @llvm.aarch64.sve.cnth(i32 9)
102 ; CHECK-NEXT: [[OUT:%.*]] = shl i64 [[CNT]], 2
150 ; CHECK-NEXT: [[CNT:%.*]] = call i64 @llvm.aarch64.sve.cntw(i32 8)
151 ; CHECK-NEXT: [[OUT:%.*]] = mul i64 [[CNT]], 3
161 ; CHECK-NEXT: [[CNT:%.*]] = call i64 @llvm.aarch64.sve.cntw(i32 9)
162 ; CHECK-NEXT: [[OUT:%.*]] = shl i64 [[CNT]], 2
212 ; CHECK-NEXT: [[CNT:%.*]] = call i64 @llvm.aarch64.sve.cntd(i32 8)
213 ; CHECK-NEXT: [[OUT:%.*]] = mul i64 [[CNT]], 3
223 ; CHECK-NEXT: [[CNT:%.*]] = call i64 @llvm.aarch64.sve.cntd(i32 9)
224 ; CHECK-NEXT: [[OUT:%.*]] = shl i64 [[CNT]], 2
/llvm-project-15.0.7/llvm/test/FileCheck/
H A Dcheck-ignore-case.txt11 # RUN: FileCheck --ignore-case --check-prefix=CNT --input-file=%s %s
37 # CNT-COUNT-6: LOop {{[0-9]}}
38 # CNT-NOT: loop
39 # CNT-NEXT: break
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dbarrier.ll11 ; CHECK: ld.param.u32 [[CNT:%r[0-9]+]], [barrier_sync_param_1];
13 ; CHECK: barrier.sync [[ID]], [[CNT]];
17 ; CHECK: barrier.sync 3, [[CNT]];
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-vscale.ll125 ; CHECK: cnth [[CNT:x[0-9]+]]
126 ; CHECK: neg x0, [[CNT]]
157 ; CHECK: cntw [[CNT:x[0-9]+]]
158 ; CHECK: neg x0, [[CNT]]
189 ; CHECK: cntd [[CNT:x[0-9]+]]
190 ; CHECK: neg x0, [[CNT]]
H A Dsve-bit-counting.ll55 ; CNT
H A Dsve-intrinsics-counting-bits.ll102 ; CNT
H A Dsve-fixed-length-bit-counting.ll369 ; CNT
/llvm-project-15.0.7/llvm/test/Transforms/ConstraintElimination/
H A Dtransfer-signed-facts-to-unsigned.ll163 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CNT:%.*]], -1
190 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CNT:%.*]], -2
217 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CNT:%.*]], 0
246 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
273 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[CNT:%.*]], 0
275 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
306 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
337 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
397 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
429 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[CNT]] to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dintrinsics.ll75 ; CHECK-NEXT: [[CNT:%.*]] = xor i1 [[ARG:%.*]], true
76 ; CHECK-NEXT: ret i1 [[CNT]]
92 ; CHECK-NEXT: [[CNT:%.*]] = xor <2 x i1> [[ARG:%.*]], <i1 true, i1 true>
93 ; CHECK-NEXT: ret <2 x i1> [[CNT]]
131 ; CHECK-NEXT: ret i32 [[CNT]]
142 ; CHECK-NEXT: ret <2 x i32> [[CNT]]
192 ; CHECK-NEXT: [[CNT:%.*]] = xor i1 [[ARG:%.*]], true
193 ; CHECK-NEXT: ret i1 [[CNT]]
210 ; CHECK-NEXT: ret <2 x i1> [[CNT]]
248 ; CHECK-NEXT: ret i8 [[CNT]]
[all …]
H A Dctpop.ll52 ; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[ARG:%.*]]), !range [[RNG0:![0-9]+]]
53 ; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[CNT]], 2
80 ; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[AND]])
81 ; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i32> [[CNT]], <i32 3, i32 3>
142 ; CHECK-NEXT: [[R:%.*]] = and i7 [[CNT]], 1
178 ; CHECK-NEXT: [[CNT:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[NEG]])
179 ; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[CNT]], <i32 1, i32 undef>
309 ; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 5, [[CNT]]
320 ; CHECK-NEXT: [[RES:%.*]] = sub i8 [[B:%.*]], [[CNT]]
342 ; CHECK-NEXT: store <2 x i32> [[CNT]], <2 x i32>* [[P:%.*]], align 8
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A D2011-11-01-lftrptr.ll157 ; PTR64-NEXT: [[CNT:%.*]] = sub i32 [[EI]], [[BI]]
158 ; PTR64-NEXT: [[GUARD:%.*]] = icmp ult i32 0, [[CNT]]
185 ; PTR32-NEXT: [[CNT:%.*]] = sub i32 [[EI]], [[BI]]
186 ; PTR32-NEXT: [[GUARD:%.*]] = icmp ult i32 0, [[CNT]]
189 ; PTR32-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* null, i32 [[CNT]]
237 ; PTR64-NEXT: [[CNT:%.*]] = sub i32 [[EI]], [[BI]]
238 ; PTR64-NEXT: [[GUARD:%.*]] = icmp ult i32 [[BI]], [[CNT]]
248 ; PTR64-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IVNEXT]], [[CNT]]
262 ; PTR32-NEXT: [[CNT:%.*]] = sub i32 [[EI]], [[BI]]
263 ; PTR32-NEXT: [[GUARD:%.*]] = icmp ult i32 [[BI]], [[CNT]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A DSROA-after-loop-unrolling.ll27 ; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[CNT:%.*]], 1
28 ; CHECK-NEXT: [[INC_1:%.*]] = add nsw i32 [[CNT]], 2
29 ; CHECK-NEXT: [[INC_2:%.*]] = add nsw i32 [[CNT]], 3
30 ; CHECK-NEXT: [[INC_3:%.*]] = add nsw i32 [[CNT]], 4
31 ; CHECK-NEXT: [[INC_4:%.*]] = add nsw i32 [[CNT]], 5
32 ; CHECK-NEXT: [[INC_5:%.*]] = add nsw i32 [[CNT]], 6
/llvm-project-15.0.7/llvm/test/FileCheck/dump-input/
H A Dannotations.txt98 ; RUN: | FileCheck -match-full-lines %s -check-prefixes=CNT,CNT-Q \
102 ; RUN: | FileCheck -match-full-lines %s -check-prefixes=CNT,CNT-V \
106 ; RUN: | FileCheck -match-full-lines %s -check-prefixes=CNT,CNT-V \
110 ; CNT: {{.*}}error:{{.*}}
112 ; CNT: <<<<<<
113 ; CNT-NEXT: 1: pete
114 ; CNT-V-NEXT: count:1'0 ^~~~
115 ; CNT-NEXT: 2: repete
116 ; CNT-V-NEXT: count:1'1 ^~~~
124 ; CNT-NEXT: >>>>>>
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dnoalias-calls2.ll12 ; CHECK-SAME: (i32* noalias [[P0:%.*]], i32* noalias [[P1:%.*]], i32 [[CNT:%.*]]) {
20 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CNT]], 0
69 ; CHECK-SAME: (i32* noalias [[P0:%.*]], i32* noalias [[P1:%.*]], i32 [[CNT:%.*]]) {
82 ; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[CNT]], 0
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td601 bits<4> CNT;
1299 let CNT = 0;
1303 let CNT = 0;
1308 let CNT = 0;
1313 let CNT = 0;
1317 let CNT = 0;
1321 let CNT = 0;
1326 let CNT = 0;
1330 let CNT = 0;
1335 let CNT = 0;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
H A DAArch64SchedCyclone.td504 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
H A DAArch64SchedTSV110.td648 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
H A DAArch64SchedKryoDetails.td501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
H A DAArch64SchedAmpere1.td1055 (instregex "^(CLS|CLZ|CNT)v")>;
H A DAArch64SchedNeoverseN2.td1504 (instregex "^(CNT|DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI$",
1641 def : InstRW<[N2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$")>;
H A DAArch64SchedThunderX2T99.td1364 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
H A DAArch64SchedThunderX3T110.td1471 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td110 (instregex "CNT(L|T)Z(D|W)(8)?(_rec)?$"),
/llvm-project-15.0.7/clang/lib/Headers/
H A Daltivec.h3175 #define __vec_ldrmb(PTR, CNT) vec_xl_len_r((const unsigned char *)(PTR), (CNT)) argument
3176 #define __vec_strmb(PTR, CNT, VAL) \ argument
3177 vec_xst_len_r((VAL), (unsigned char *)(PTR), (CNT))

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