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Searched refs:CMP1 (Results 1 – 25 of 193) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcompare-udiv.ll7 ; CHECK-NEXT: ret i1 [[CMP1]]
17 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
27 ; CHECK-NEXT: ret i1 [[CMP1]]
47 ; CHECK-NEXT: ret i1 [[CMP1]]
67 ; CHECK-NEXT: ret i1 [[CMP1]]
105 ; CHECK-NEXT: ret i1 [[CMP1]]
144 ; CHECK-NEXT: ret i1 [[CMP1]]
164 ; CHECK-NEXT: ret i1 [[CMP1]]
184 ; CHECK-NEXT: ret i1 [[CMP1]]
204 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
H A Dicmp-select.ll10 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
23 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
37 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
51 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
67 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
68 ; CHECK-NEXT: ret i1 [[CMP1]]
79 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
95 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
98 ; CHECK-NEXT: ret i1 [[CMP1]]
208 ; CHECK-NEXT: call void @use.i1(i1 [[CMP1]])
[all …]
H A Dprevent-cmp-merge.ll11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
13 ; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]
27 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 10
29 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
43 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[XOR]], 0
45 ; CHECK-NEXT: [[SEL:%.*]] = xor i1 [[CMP1]], [[CMP2]]
59 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]
61 ; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]
75 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]
77 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
H A Dashr-lshr.ll55 ; CHECK-NEXT: ret i32 [[CMP1]]
115 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
127 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
139 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
151 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
163 ; CHECK-NEXT: ret i32 [[CMP1]]
187 ; CHECK-NEXT: ret i32 [[CMP1]]
199 ; CHECK-NEXT: ret i32 [[CMP1]]
211 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
223 ; CHECK-NEXT: ret <2 x i32> [[CMP1]]
[all …]
H A Dclamp-to-minmax.ll187 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ole float [[X]], 0.000000e+00
202 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 0.000000e+00
224 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 1.000000e+00
239 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp olt float [[X]], 1.000000e+00
255 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ole float [[X]], 1.000000e+00
270 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ole float [[X]], 1.000000e+00
286 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt float [[X]], 2.550000e+02
301 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ogt float [[X]], 2.550000e+02
317 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oge float [[X]], 2.550000e+02
332 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp oge float [[X]], 2.550000e+02
[all …]
H A Ddont-distribute-phi.ll10 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
11 ; CHECK-NEXT: br i1 [[CMP1]], label [[BB_THEN:%.*]], label [[BB_ELSE:%.*]]
20 ; CHECK-NEXT: [[XOR1:%.*]] = xor i1 [[CMP1]], true
47 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
48 ; CHECK-NEXT: br i1 [[CMP1]], label [[BB_THEN:%.*]], label [[BB_ELSE:%.*]]
57 ; CHECK-NEXT: [[XOR1:%.*]] = xor i1 [[CMP1]], true
H A Dmerge-icmp.ll168 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[TRUNC]], 127
169 ; CHECK-NEXT: call void @use.i1(i1 [[CMP1]])
172 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
187 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[TRUNC]], 127
191 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
240 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[TRUNC]], 127
243 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
260 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
277 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
294 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dand-icmps-same-ops.ll10 ; CHECK-NEXT: ret i1 [[CMP1]]
31 ; CHECK-NEXT: ret i1 [[CMP1]]
52 ; CHECK-NEXT: ret i1 [[CMP1]]
73 ; CHECK-NEXT: ret i1 [[CMP1]]
94 ; CHECK-NEXT: ret i1 [[CMP1]]
127 ; CHECK-NEXT: ret i1 [[CMP1]]
260 ; CHECK-NEXT: ret i1 [[CMP1]]
369 ; CHECK-NEXT: ret i1 [[CMP1]]
380 ; CHECK-NEXT: ret i1 [[CMP1]]
391 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
H A Dor-icmps-same-ops.ll160 ; CHECK-NEXT: ret i1 [[CMP1]]
181 ; CHECK-NEXT: ret i1 [[CMP1]]
202 ; CHECK-NEXT: ret i1 [[CMP1]]
223 ; CHECK-NEXT: ret i1 [[CMP1]]
236 ; CHECK-NEXT: ret i1 [[CMP1]]
268 ; CHECK-NEXT: ret i1 [[CMP1]]
476 ; CHECK-NEXT: ret i1 [[CMP1]]
528 ; CHECK-NEXT: ret i1 [[CMP1]]
716 ; CHECK-NEXT: ret i1 [[CMP1]]
800 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
H A Dselect-implied.ll8 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
9 ; CHECK-NEXT: br i1 [[CMP1]], label [[TAKEN:%.*]], label [[END:%.*]]
33 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
58 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[A:%.*]], 10
149 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[A:%.*]], 10
176 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[A:%.*]], 0
178 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP1]], [[CMP2]]
205 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], 0
207 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP1]], [[CMP2]]
233 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
[all …]
H A Dlogic-of-fcmps.ll53 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord float [[X:%.*]], [[Y:%.*]]
54 ; CHECK-NEXT: ret i1 [[CMP1]]
65 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp ord double [[Y:%.*]], [[X:%.*]]
66 ; CHECK-NEXT: ret i1 [[CMP1]]
77 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
88 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
142 ; CHECK-NEXT: [[CMP1:%.*]] = fcmp uno float [[X:%.*]], [[Y:%.*]]
143 ; CHECK-NEXT: ret i1 [[CMP1]]
154 ; CHECK-NEXT: ret i1 [[CMP1]]
165 ; CHECK-NEXT: ret <2 x i1> [[CMP1]]
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dmonotonic-phi.ll11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
36 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
63 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
88 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
113 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
140 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
165 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
192 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
217 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
241 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A]], [[N:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dselect-opt.ll9 ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
12 ; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]]
27 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
28 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
43 ; GCN: s_cselect_b64 [[CMP1:s\[[0-9]+:[0-9]+\]]], -1, 0
46 ; GCN: s_and_b64 vcc, [[CMP1]], [[CMP2]]
62 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
80 ; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]]
97 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
115 ; GCN: s_or_b64 vcc, [[CMP1]], [[CMP2]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dmetadata-simplify.ll13 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32* [[LOAD1]], null
14 ; CHECK-NEXT: ret i1 [[CMP1]]
38 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32* [[LOAD1]], null
39 ; CHECK-NEXT: ret i1 [[CMP1]]
64 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[LOAD1]], 999
65 ; CHECK-NEXT: ret i1 [[CMP1]]
89 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[LOAD1]], 999
90 ; CHECK-NEXT: ret i1 [[CMP1]]
114 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LOAD1]], 999
115 ; CHECK-NEXT: ret i1 [[CMP1]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/ARM/
H A Dbranch-fold-threshold.ll11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
44 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
77 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[ADD]], [[B:%.*]]
110 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
143 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
178 ; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
191 ; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
226 ; THUMB-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
239 ; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
318 ; ARM-NEXT: [[CMP1:%.*]] = icmp slt i32 [[ADD]], [[B:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcmpxchg-O0.ll23 ; CHECK: uxtb [[CMP1:r[0-9]+]], [[DESIRED]]
24 ; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
25 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
47 ; CHECK: uxth [[CMP1:r[0-9]+]], [[DESIRED]]
48 ; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
49 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
71 ; CHECK: sub{{(s)?}} [[CMP1:r[0-9]+]], [[OLD]], [[DESIRED]]
72 ; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/X86/
H A Dextract-cmp-binop.ll9 ; SSE-NEXT: [[CMP1:%.*]] = fcmp olt double [[E1]], 4.200000e+01
11 ; SSE-NEXT: [[R:%.*]] = and i1 [[CMP1]], [[CMP2]]
35 ; SSE-NEXT: [[R:%.*]] = or i1 [[CMP1]], [[CMP2]]
75 ; SSE-NEXT: [[CMP1:%.*]] = icmp eq i32 [[E1]], 42
77 ; SSE-NEXT: [[R:%.*]] = add i1 [[CMP1]], [[CMP2]]
101 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[E1]], 42
103 ; CHECK-NEXT: [[R:%.*]] = and i1 [[CMP1]], [[CMP2]]
120 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[E1]], 42
122 ; CHECK-NEXT: [[R:%.*]] = and i1 [[CMP1]], [[CMP2]]
139 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[E1]], 42
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dconflict.ll11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A:%.*]], 5
12 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
38 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A:%.*]], 5
39 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
58 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[A:%.*]], 5
59 ; CHECK-NEXT: br i1 [[CMP1]], label [[DEAD:%.*]], label [[EXIT:%.*]]
H A Dselect.ll108 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[PVAL]], 255
109 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
133 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[PVAL]], 255
134 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
159 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[PVAL]], 255
160 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
188 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[PVAL]], 255
189 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
216 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[PVAL]], 255
217 ; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[EXIT:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Dloop-invariant-conditions.ll11 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[START:%.*]], -1
12 ; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_END:%.*]], label [[LOOP]]
34 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sle i64 [[START:%.*]], -1
64 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[START]], -1
65 ; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_END]], label [[LOOP]]
99 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i64 [[START]], -1
134 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[START]], 100
169 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[START]], 100
202 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[START:%.*]], -1
237 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[INDVARS_IV]], -1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dcommon-code-hoisting.ll50 ; HOIST-NEXT: [[CMP1:%.*]] = call i1 @gen1()
52 ; HOIST-NEXT: br i1 [[CMP1]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
66 ; NOHOIST-NEXT: [[CMP1:%.*]] = call i1 @gen1()
67 ; NOHOIST-NEXT: br i1 [[CMP1]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
119 ; HOIST-NEXT: [[CMP1:%.*]] = fcmp olt float [[VALUE]], [[MINIMUM_VALUE:%.*]]
120 ; HOIST-NEXT: [[MINIMUM_VALUE_VALUE:%.*]] = select i1 [[CMP1]], float [[MINIMUM_VALUE]], float […
127 ; NOHOIST-NEXT: [[CMP1:%.*]] = fcmp olt float [[VALUE]], [[MINIMUM_VALUE:%.*]]
128 ; NOHOIST-NEXT: [[MINIMUM_VALUE_VALUE:%.*]] = select i1 [[CMP1]], float [[MINIMUM_VALUE]], float…
H A Dbranch-fold-three.ll12 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[S]], [[T]]
13 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_END6]]
54 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sge i32 [[S]], [[T]]
55 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_END6]]
96 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[T]], [[S]]
97 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_END6]]
138 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sle i32 [[T]], [[S]]
139 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_END6]]
180 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[T]], [[S]]
181 ; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_END6]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Drlev-add-me.ll16 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
17 ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
54 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
55 ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
101 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
102 ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
155 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
156 ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
199 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[V]], 0
200 ; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT1:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/
H A Dcommute.ll131 ; CHECK-NEXT: [[CMP2:%.*]] = xor i1 [[CMP1]], true
176 ; CHECK-NEXT: [[CMP2:%.*]] = xor i1 [[CMP1]], true
223 ; CHECK-NEXT: [[CMP2:%.*]] = xor i1 [[CMP1]], true
269 ; CHECK-NEXT: [[CMP2:%.*]] = xor i1 [[CMP1]], true
308 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sge i8 [[A]], 0
325 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i8 [[A]], 0
346 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 [[A]], 0
365 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 [[A]], 0
386 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i8 [[A]], 0
405 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i8 [[A]], 0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dhorizontal-store.ll21 ; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
22 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i32 [[TMP2]], i32 [[TMP3]]
27 ; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i32 3, i32 4
62 ; GFX9-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
63 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i64 [[TMP2]], i64 [[TMP3]]
68 ; GFX9-NEXT: [[STORE_SELECT:%.*]] = select i1 [[CMP1]], i64 3, i64 4
105 ; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast ogt float [[TMP2]], [[TMP3]]
156 ; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast olt double [[TMP2]], [[TMP3]]
204 ; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[ELT1]], [[V1:%.*]]
206 ; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], i32 [[EX0]], i32 [[V1]]
[all …]

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