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Searched refs:CMP0 (Results 1 – 25 of 42) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmubuf-legalize-operands.ll19 ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
36 ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
60 ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
77 ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
98 ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
115 ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
147 ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
167 ; W64: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[CMP0]]
191 ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
211 ; W32: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[CMP0]]
[all …]
H A Dmubuf-legalize-operands.mir25 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[STMP0]], [[VRSRC]].sub0_sub1, implicit $…
30 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
56 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
102 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[STMP0]], [[VRSRC]].sub0_sub1, implicit $…
107 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
133 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
179 # W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[STMP0]], [[VRSRC]].sub0_sub1, implicit $…
184 # W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
210 # W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
298 # W64-NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
[all …]
H A Dimage-sample-waterfall.ll13 ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
17 ; GCN-NEXT: s_and_b64 [[AND0:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
46 ; GCN-NEXT: v_cmp_eq_u64_e32 [[CMP0:vcc]], s[[[SREG0]]:[[SREG1]]], v[[[VREG0]]:[[VREG1]]]
48 ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
H A Dcontrol-flow-fastregalloc.ll22 ; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, s{{[0-9]+}}
33 …nd_b64 s[[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]], [[CMP0]]
91 ; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], v0, s{{[0-9]+}}
106 …EXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]
169 ; GCN: v_cmp_ne_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], v0, [[ZERO]]
172 …EXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]], s[[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]], [[CMP0]]
183 ; GCN: s_mov_b64 exec, [[CMP0]]
H A Dloop_break.ll16 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
17 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
93 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
94 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
184 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
185 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
272 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
273 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
360 ; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
361 ; OPT-NEXT: br i1 [[CMP0]], label [[BB4:%.*]], label [[FLOW]]
[all …]
H A Dsitofp.f16.ll98 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
100 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
H A Duitofp.f16.ll97 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
99 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
H A Dfdiv.f64.ll19 ; SI-DAG: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}
20 ; SI-DAG: s_xor_b64 vcc, [[CMP0]], vcc
H A Dtrunc-cmp-constant.ll137 ; XSI: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], [[TMP]], 0{{$}}
138 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_assume.ll6 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i16 [[Y:%.*]], 16
7 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP0]])
24 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i16 [[X:%.*]], 0
26 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP0]])
46 ; CHECK-NEXT: [[CMP0:%.*]] = icmp slt i16 [[X:%.*]], 32767
49 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP0]])
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dpeel-loop.ll8 ; CHECK: %[[CMP0:.*]] = icmp sgt i32 %k, 0
9 ; CHECK: br i1 %[[CMP0]], label %[[NEXT0:.*]], label %for.end
64 ; CHECK: %[[CMP0:.*]] = icmp sgt i32 %k, 0
65 ; CHECK: br i1 %[[CMP0]], label %[[NEXT0:.*]], label %for.end
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Deliminate-exit.ll7 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i64 [[N:%.*]], [[M:%.*]]
8 ; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
43 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ugt i64 [[N:%.*]], [[M:%.*]]
44 ; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
79 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ule i64 [[N:%.*]], [[M:%.*]]
80 ; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
116 ; CHECK-NEXT: [[CMP0:%.*]] = icmp uge i64 [[N:%.*]], [[M:%.*]]
117 ; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
154 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i64 [[N:%.*]], 20
155 ; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dvector.ll22 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X0]], [[Y0]]
23 ; CHECK-NEXT: br i1 [[CMP0]], label [[IF:%.*]], label [[ENDIF:%.*]]
H A Dcrash_reordering_undefs.ll8 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 undef, [[OR0]]
9 ; CHECK-NEXT: [[ADD0:%.*]] = select i1 [[CMP0]], i32 65536, i32 65537
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dphi-of-ops-move-block.ll13 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[STOREMERGE]], 0
14 ; CHECK-NEXT: br i1 [[CMP0]], label [[LR_PH:%.*]], label [[CRITEDGE]]
23 ; CHECK-NEXT: [[PHIOFOPS:%.*]] = phi i1 [ [[CMP0]], [[BB1]] ], [ true, [[LR_PH]] ]
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dswitch.ll87 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i32 [[MUL]], 127
88 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP0]], i32 [[MUL]], i32 127
139 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i32 [[MUL]], 127
140 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP0]], i32 [[MUL]], i32 127
193 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i32 [[MUL]], 127
194 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP0]], i32 [[MUL]], i32 127
/llvm-project-15.0.7/llvm/test/Transforms/DeadArgElim/
H A Dfct_ptr.ll13 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 (i32, i32, i32)* [[FCT_PTR:%.*]], @external_fct
14 ; CHECK-NEXT: br i1 [[CMP0]], label [[CALL_EXT:%.*]], label [[CHK2:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dextract-cost.ll33 ; CHECK-NEXT: [[CMP0:%.*]] = extractelement <4 x i1> [[CMP]], i32 0
37 ; CHECK-NEXT: [[CMP0_NOT:%.*]] = xor i1 [[CMP0]], true
/llvm-project-15.0.7/llvm/test/Transforms/MergeICmps/X86/
H A Dgep-references-bb.ll20 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[L0]], [[R0]]
21 ; CHECK-NEXT: br i1 [[CMP0]], label %"bb1+bb2", label [[FINAL:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/CorrelatedValuePropagation/
H A Dicmp.ll228 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sge i32 [[A:%.*]], 0
230 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
259 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sge i32 [[A:%.*]], 0
261 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
371 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sge i32 [[A:%.*]], 0
373 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
404 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
435 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
464 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
495 ; CHECK-NEXT: [[BR:%.*]] = and i1 [[CMP0]], [[CMP1]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LICM/
H A Dsink-foldable.ll11 ; CHECK-NEXT: [[CMP0:%.*]] = icmp slt i32 0, [[J:%.*]]
12 ; CHECK-NEXT: br i1 [[CMP0]], label [[FOR_BODY_LR_PH:%.*]], label [[RETURN:%.*]]
167 ; CHECK-NEXT: [[CMP0:%.*]] = icmp slt i64 0, [[J:%.*]]
168 ; CHECK-NEXT: br i1 [[CMP0]], label [[FOR_BODY_LR_PH:%.*]], label [[RETURN:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/NaryReassociate/
H A Dnary-req.ll75 ; CHECK-NEXT: [[CMP0:%.*]] = icmp slt i32 [[D2:%.*]], [[D1:%.*]]
76 ; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 [[D1]], i32 [[D2]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dassume.ll632 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
634 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP0]], [[CMP1]]
669 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
671 ; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
706 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
708 ; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP0]], [[CMP1]]
746 ; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
748 ; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
H A Ddemorgan.ll460 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
462 ; CHECK-NEXT: [[TMP1:%.*]] = or i1 [[CMP0]], [[CMP1]]
476 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
478 ; CHECK-NEXT: [[AND:%.*]] = select i1 [[CMP0]], i1 true, i1 [[CMP1]]
/llvm-project-15.0.7/mlir/test/Conversion/ShapeToStandard/
H A Dshape-to-standard.mlir368 // CHECK: %[[CMP0:.*]] = arith.cmpi ugt, %[[RANK1]], %[[RANK0]] : index
369 // CHECK: %[[LARGER_DIM:.*]] = arith.select %[[CMP0]], %[[RANK1]], %[[RANK0]] : index
458 // CHECK: %[[CMP0:.*]] = arith.cmpi ugt, %[[RANK1]], %[[RANK0]] : index
459 // CHECK: %[[LARGER_DIM:.*]] = arith.select %[[CMP0]], %[[RANK1]], %[[RANK0]] : index
550 // CHECK: %[[CMP0:.*]] = arith.cmpi ugt, %[[RANK1]], %[[RANK0]] : index
551 // CHECK: %[[LARGER_DIM:.*]] = arith.select %[[CMP0]], %[[RANK1]], %[[RANK0]] : index

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