| /llvm-project-15.0.7/lld/test/MachO/ |
| H A D | objc-imageinfo.s | 79 # HAS-CAT-CLS: Contents of (__DATA_CONST,__objc_imageinfo) section
80 # HAS-CAT-CLS: 00 00 00 40 00 00 00
81 # HAS-CAT-CLS-EMPTY:
83 # NO-CAT-CLS: Contents of (__DATA_CONST,__objc_imageinfo) section
84 # NO-CAT-CLS: 00 00 00 00 00 00 00
85 # NO-CAT-CLS-EMPTY:
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | LoopCacheAnalysis.cpp | 160 unsigned CLS, in hasSpacialReuse() argument
202 bool InSameCacheLine = (Diff->getValue()->getSExtValue() < CLS); in hasSpacialReuse()
274 unsigned CLS) const { in computeRefCost()
293 if (isConsecutive(L, Stride, CLS)) { in computeRefCost()
299 const SCEV *CacheLineSize = SE.getConstant(WiderType, CLS); in computeRefCost()
464 unsigned CLS) const { in isConsecutive()
491 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive()
618 unsigned CLS = TTI.getCacheLineSize(); in populateReferenceGroups() local
655 R->hasSpacialReuse(Representative, CLS, AA); in populateReferenceGroups()
|
| /llvm-project-15.0.7/clang/test/CodeGenObjCXX/ |
| H A D | arc-cxx11-member-init.mm | 26 // CHECK: [[CLS:%.*]] = load %struct._class_t*, %struct._class_t** @"OBJC_CLASSLIST_REFERENCES_$_"
27 // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[CLS]] to i8*
|
| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | LoopCacheAnalysis.h | 75 Optional<bool> hasSpacialReuse(const IndexedReference &Other, unsigned CLS,
95 CacheCostTy computeRefCost(const Loop &L, unsigned CLS) const;
113 bool isConsecutive(const Loop &L, const SCEV *&Stride, unsigned CLS) const;
|
| /llvm-project-15.0.7/clang/test/CodeGenObjC/ |
| H A D | gnu-init.m | 77 …K-WIN-DAG: @"__start_.objcrt$CLS" = linkonce_odr hidden global %.objc_section_sentinel zeroinitial…
78 …ECK-WIN-DAG: @"__stop.objcrt$CLS" = linkonce_odr hidden global %.objc_section_sentinel zeroinitial…
91 …t$SEL", %.objc_section_sentinel* @"__start_.objcrt$CLS", %.objc_section_sentinel* @"__stop.objcrt$…
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPatterns.td | 19 // in which the first operand has class CLS and which the second operand
56 // Record that INSN performs insertion TYPE into a register of class CLS.
148 // registers in CLS against zero. The instruction has separate R1 and R2
157 // on registers of class CLS.
|
| /llvm-project-15.0.7/llvm/test/MC/AVR/ |
| H A D | inst-family-set-clr-flag.s | 58 ; CLS
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 152 // CLS,CLZ,RBIT,REV,REV16,REV32
504 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| H A D | AArch64SchedTSV110.td | 410 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
648 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
|
| H A D | AArch64SchedFalkorDetails.td | 922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| H A D | AArch64SchedAmpere1.td | 983 def : InstRW<[Ampere1Write_1cyc_1B], (instregex "CLS(W|X)")>;
1055 (instregex "^(CLS|CLZ|CNT)v")>;
|
| H A D | AArch64SchedKryoDetails.td | 495 (instregex "(CLS|CLZ)(W|X)r")>;
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
|
| H A D | AArch64SchedThunderX2T99.td | 560 def : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$",
1364 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
|
| H A D | AArch64SchedThunderX3T110.td | 820 (instregex "^CLS(W|X)r$", "^CLZ(W|X)r$")>;
1471 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
|
| H A D | AArch64SchedA64FX.td | 947 def : InstRW<[A64FXWrite_2Cyc_GI0], (instregex "^CLS(W|X)r$",
1750 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
|
| H A D | AArch64SchedNeoverseN2.td | 1641 def : InstRW<[N2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$")>;
|
| H A D | AArch64InstrInfo.td | 2134 defm CLS : OneOperandData<0b101, "cls">;
4307 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve-intrinsics-counting-bits.ll | 6 ; CLS
|
| H A D | sve-unary-movprfx.ll | 243 ; CLS (sve_int_un_pred_arit_1)
|
| /llvm-project-15.0.7/clang/lib/Frontend/Rewrite/ |
| H A D | RewriteModernObjC.cpp | 6393 CLS = 0x0, enumerator
7108 flags = CLS; in RewriteObjCClassMetaData()
|